Assigned homework is due the following
class period, unless otherwise noted.
You may pick up your graded homework and quizzes from the shelves marked for EE 261 outside your instructor’s office. Solutions will promptly be made available to you after homework and quizzes are graded. These will be posted in the display outside office 616 Cobleigh Hall as long as room allows. After solutions are taken down from the display, the answers will be made available upon request.
Please:
Put your name and date due in
the upper right hand corner of first page.
Do the Homework in order.
Staple multiple pages together.
Remove all spiral notebook fringes.
Be neat. Illegible homework will be marked as
incorrect.
Underline
or put a box around the answer to make it
obvious to the grader.
This
page was last updated: 4/29/2008
Date
|
Week
|
Lecture Topics
|
Reading (before class) |
Lecture Notes
and downloads
|
Homework Problems |
Date HW is Due |
W
1/16
|
1
|
Introduction, expectations,
resources, protocol |
Preface, Ch 1 |
|
1.5, 1.6 |
F
1/18
|
F
1/18
|
1
|
Positional number systems, binary point, octal,
hexadecimal, converting between number systems |
2.1-2.3 |
|
2.2(e), 2.3(e), 2.5(a, d,
f) |
W
1/23
|
M 1/21
|
2
|
Martin Luther King Holiday – No
classes
|
|
|
|
|
W
1/23
|
2
|
Converting between number
systems, adding and subtracting positive numbers |
2.4-2.5 |
|
2.6(a, d, f), 2.7(c),
2.8(a), 2.9(b), 2.10(a) |
F
1/25
|
F 1/25
|
2
|
Signed magnitude, two’s
complement adding and subtracting, overflow, Binary codes |
2.6, 2.10-11, 2.16 |
|
2.11(signed-magnitude &
two’s-complement), 2.12(a, d) |
M
1/28
|
M
1/28
|
3
|
Gray and
other codes. Logic signals,
Logic gates |
3.1 – 3.3 |
|
2.18(d), 3.1, 3.4 |
W
1/30
|
W
1/30
|
3
|
Families, MOSFET, CMOS
gates |
3.3 – 3.4 |
|
3.5, 3.7 |
F
2/1
|
F
2/1
|
3
|
Gate Transistors, Static
Behavior, Datasheet Specs |
3.4 |
3.11, 3.15, 3.19 |
M 2/4
|
|
M
2/4
|
4
|
Static Behavior , Dynamic
Behavior |
3.5 |
|
3.21, 3.23, 3.27(c, e) |
W
2/6
|
W
2/6
|
4
|
Dynamic Behavior |
3.6 |
|
3.29, 3.32, 3.34 |
F
2/8
|
F
2/8
|
4
|
Review for Exam |
|
|
Study for Exam |
|
M
2/11
|
5
|
Exam 1 |
Ch 1-3 |
|
|
|
W
2/13
|
5
|
Exam
Solutions, Axioms and theorems of Boolean algebra |
4.1 |
|
No homework |
F
2/15
|
F
2/15
|
5
|
Theorem proofs |
|
|
4.1, 4.2, 4.6(a), |
W
2/20
|
M 2/18
|
6
|
PRESIDENT’S DAY - NO CLASSES |
|
|
|
|
W
2/20
|
6
|
Using Theorems to reduce
logic expressions |
4.2
|
|
4.7(a), 4.8(c), |
F
2/22
|
F
2/22
|
6
|
DeMorgan’s Theorem, Duality |
|
|
4.21, 4.23 |
M
2/25
|
M
2/25
|
7
|
Sum-of-products,
Product-of-sums |
4.2 |
|
4.9(c, d), 4.10(b, d, f) |
W
2/27
|
W 2/27
|
7
|
Karnaugh maps |
4.3
|
|
4.11, 4.13 |
F
2/29
|
F
2/29
|
7
|
Karnaugh maps |
4.3
|
|
|
M
3/3
|
M
3/3
|
8
|
Minimization
methods continued , Review for exam |
|
|
Study for Exam |
|
W
3/5
|
8
|
Exam 2 |
Ch 1-4.3 |
|
|
|
F
3/7
|
8
|
Exam Solutions |
|
|
No Homework |
M
3/17
|
M 3/10
|
9
|
SPRING BREAK – No Classes |
|
|
|
|
W 3/12
|
9
|
SPRING BREAK – No Classes |
|
|
|
|
F 3/14
|
9
|
SPRING BREAK – No Classes
|
|
|
|
|
M
3/17
|
10
|
Circuit
synthesis, Timing Hazards
|
4.4 |
|
4.14 (all) |
W
3/19
|
W
3/19
|
10
|
Documentation standards,
active levels, bubble-to-bubble logic, active levels |
6.1
|
|
4.19 (a, c, e, g) |
M
3/24
|
F 3/21
|
10
|
University Day
-No classes |
|
|
|
|
M 3/24
|
11
|
PLD’s, 3-states, Decoders, Encoders |
6.2-8 |
|
6.9, 6.10, 6.20 (a, f) |
W
3/26
|
W
3/26
|
11
|
MUX, parity, comparators, ALU’s |
6.9 – 6.11 |
|
6.24, 6.31 |
F
3/28
|
F
3/28
|
11
|
Bistable and metastable behavior |
7.1 |
|
6.43 (design one circuit
with four outputs), 6.68 |
M
3/31
|
M
3/31
|
12
|
Review for exam |
|
|
Study for Exam |
|
W
4/2
|
12
|
Exam 3 |
Ch 1-4, 6 |
|
|
|
F
4/4
|
12
|
Exam Solutions, Latches |
7.1 – 7.2 |
|
7.1, 7.4, 7.5 |
M
4/7
|
M
4/7
|
13
|
Flip-flops |
7.2 |
|
7.6, 7.7 |