Project Overview
Design of a Processor-to-Memory I/O interface with Automatic Recovery of Line Failures (Fall 2009)

Sponsor: NASA Radiation Hardened Electronics for Space Explorations (RHESE) Program
Advisor: Prof. Brock J. LaMeres
Team: Jeffrey Bahr, Devin Mikes, Sam Harkness

In this project the senior design team will design and prototype a microprocessor memory interface that has the ability to automatically recover from a failure on one of the signal lines. The system will be prototyped using two Xilinx V5 FPGA evaluation boards. One FPGA board will contain a soft microprocessor (picoBlaze) and the other will contain the computer memory. The physical interface between the microprocessor will consist of a simple ribbon cable. An I/O interface system will be designed that will utilize spare conductors on the ribbon cable to recover from a failure on one of the signal lines. The system will be able to dynamically detect a failure on the I/O interface (i.e., stuck low, stuck high, or open) and move that effected signal line to one of the spare conductors in the interface. The system will be designed to seamlessly interface with the existing microprocessor and memory devices. The I/O system will need to be able to halt the processor in the event of a failure while the dynamic reallocation of the I/O lines is accomplished and then return the system to normal operation without a noticeable degradation to the performance of the computing system.

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