Montana State University
Academics | Administration | Admissions | A-Z Index | Directories

Montana State Universityspacer Mountains and Minds
MSU AcademicsspacerMSU AdministrationspacerMSU AdmissionsspacerMSU A-Z IndexspacerMSU Directoriesspacer
 


Contact Us
Brock J. LaMeres
Assistant Professor
533 Cobleigh Hall
Bozeman, MT 59717

Tel: (406) 994-5987
Fax: (406) 994-5958
lameres@ece.montana.edu

ECE Department
Montana State University
610 Cobleigh Hall
Bozeman, MT 59717

Tel: (406) 994-2505
Fax: (406) 994-5958
eedept@ee.montana.edu www.coe.montana.edu/ee

> College of Engineering > Electrical & Computer Engineering Department
LaMeres' Vitae
LaMeres' 2 Page CV (PDF)

Table of Contents

  1. Education
  2. Professional Experience
  3. Teaching Experience
  4. Awards and Honors
  5. Funded Projects
  6. Consulting
  7. Publications
    1. Thesis / Dissertation
    2. Fully Refereed Journal Articles
    3. Fully Refereed Conference Proceedings
    4. Refereed Conference Proceedings
    5. Non-Refereed Publications / Trade Journals
  8. Invited Talks
  9. Patents
  10. Service
  11. Students Supervised
  12. Professional Registration
  13. Professional Membership
  14. Honorary Memberships

  1. Education

    2. B.S. Electrical Engineering
    Montana State University, Bozeman, MT.
    December 1999, G.P.A. 3.7/4.0 (highest honors)
    Senior Project: "Fuzzy Logic Voltage Controller for Synchronous Generators"
    Thesis Advisor: M.H. Nehrir
    M.S. Electrical Engineering
    University of Colorado, Colorado Springs, CO.
    May 2001, G.P.A. 4.0/4.0
    Thesis Topic: "Characterization of a Printed Circuit Board Via"
    Thesis Advisor: T.S. Kalkur
    Ph.D. Electrical Engineering
    University of Colorado, Boulder.
    December 2005, G.P.A. 4.0/4.0
    Thesis Topic: "Novel Design Techniques to Reduce SSN in VLSI Packaging"
    Thesis Advisor: Sunil. P. Khatri

  2. Professional Experience

    3. 7/06-pres Montana State University, Bozeman, MT. Assistant Professor
    I conduct research and teach courses in the area of high-speed
    digital circuit design with an emphasis on CMOS devices,
    programmable logic, and interconnect systems.

    1/99-7/06 Agilent Technologies Inc., Colo Springs, CO. R&D Engineer
    I worked in the Design Validation R&D lab. This job involved
    designing hardware for logic analyzer and mixed-signal-oscilloscope
    products. During this job, I performed the following functions:
    Probe Design: For three years I worked as the lead architect for
    Agilent's logic analyzer probing systems. This involved developing
    compensated transport systems capable of delivering 7GHz of
    bandwidth. The transport systems contained interconnect, PCBs
    cables, and custom amplifiers.
    Printed Circuit Board Design: For 4 years I designed and verified
    printed circuit boards for use in Agilent's logic analyzer
    acquisition systems (16910/11/12 & 1695x). These modules were
    capable of capturing digital data up to 2Gb/s in addition to
    having 2.3GHz of front-end analog bandwidth.
    FPGA Design: Also during my career at Agilent I designed and
    verified a variety of digital circuitry implemented in both
    Xilinx and Altera FPGA's. The circuitry was designed using a
    combination of structural and RTL modeling in Verilog HDL.
    The designs were synthesized, mapped, and placed/routed using
    the Xilinx ISE and Synplicity toolsets.
    During my career at Agilent, I specifically designed the
    following hardware:
    • Cal Adapter for the FSI-60035 RAMBUS Probe (400Mb/s)
    • E2696-10 - Stim Bd for IA64 E2696A Probe, Merced (10MHz)
    • E8033-04 - Acq Bd for the E8033/34 Probe, P4, (100MHz)
    • E8033-05 - Stim Bd for the E8033A IA32 Probe, (P4), (10MHz)
    • E8034-05 - Stim Bd for the E8034A IA32 Probe, (P4), (10MHz)
    • E8036-01 - AC Cal Bd for IA64 E8036A Probe, Itanium, (100MHz)
    • 16754-01 - Acq PCB the 16753/4/5/6 & 16950 Logic Analyzers
    • 16754-02 - ASIC Emulator using an FPGA (50MHz)
    • 16754-06 - Credit Card Stim Bd, (100MHz)
    • 16910-01 - Acq PCB for the 16910/11/12 Logic Analyzers (500Mb/s)
    • 16960-01 - Acq PCB for the 16960 Logic Analyzer (2Gb/s)
    • ET846242-01 - Stim Bd for Backside Attach BGA Probe (1Gb/s)
    • ET835584-01 - Stim Bd for GP Logic Analyzer Probes (2Gb/s)
    • ET852690-01 - Stim Bd for the E4252A FSB Probe (2.5Gb/s)
    • E5394A - Soft Touch Connectorless Probe (500Mb/s)
    • E539xA - Soft Touch to Mictor Adapter (200Mb/s)
    • E5396A - Soft Touch Connectorless Probe (500Mb/s)
    • E5398A - Soft Touch Connectorless Probe (1.5Gb/s)
    • E5404A - Soft Touch Pro Connectorless Probe (500Mb/s)
    • E5405A - Soft Touch Pro Connectorless Probe (1.5Gb/s)
    • E5406A - Soft Touch Pro Connectorless Probe (1.5Gb/s)
    • E5402A - Soft Touch Pro, Low-Profile Probe (1.5Gb/s)
    • E8060A - FSB Probe for IA32 Tigerton uP (1066Mb/s)
    • E4252-01 - Serial FSB Probe for 16960A Logic Analyzer (2Gb/s)
    • ET854492-01 - PCI Express, Gen2, Slot Interposer Probe (5Gb/s)

    8/01-12/03 University of Colorado, Adjunct Instructor
    Department of Electrical and Computer Engineering
    Colorado Springs, CO.

    5/97-12/98 Montana State University, Undergrad. Research Assistant
    Department of Electrical and Computer Engineering
    Bozeman, MT.

    5/98-8/98 Micron Technology, Inc., Test Engineer (Intern)
    Test Division
    Boise, ID.

    1/96-8/96 VeriBest, Inc., ASIC Library Development Engineer (Intern)
    ASIC Library Group
    Longmont, CO.

  3. Teaching Experience

    4. 7/06 - pres Montana State University, ECE Department.
    Bozeman, MT. Assistant Professor
    EE 261 - Introduction to Logic Circuits (S07)
    EE 367 - Logic Design (S07,S08)
    EE 371 - uP Hardware and Software Systems (F06,F07,F08)
    EE 414 - Introduction to VLSI Design (F07,F08)
    EE 461 - Digital System Design* (S08)
     
    *NOTE: EE461 is a new course that I proposed and developed.
    This course is now a part of the regular ECE curriculum.

    8/01 - 12/03 University of Colorado, ECE Department.
    Colorado Springs, CO. Adjunct Instructor
    ECE 3420 - uP System Laboratory I (F01)
    ECE 3430 - Intro to uP Systems (F02,F03)
    ECE 3440 - uP System Laboratory II (S02,S03)

  4. Awards and Honors

    • Montana Organization for Research in Energy Fellowship, Montana State University, Bozeman, 1999.
    • MONTS Undergraduate Fellowship, Montana State University, Bozeman, 1999.
    • Outstanding Graduate Student in Electrical and Computer Engineering, University of Colorado, Colorado Springs, 2001.
    • Best Paper Award, "Performance Modeling for Off-Chip Busses Considering Bandwidth and Cost", DesignCon-05. PCB & Package Co-Design Track, Feb 2005.
    • Best Paper Award, "Broadband Impedance Matching for Inductive Interconnect in VLSI Packaging", IEEE International Conference on Computer Design (ICCD). Circuit Consideration in Processor Design track, 2005.
    • 2006 Outstanding Instructor in Electrical and Computer Engineering, Montana State University, Bozeman. (voted on by students).
    • 2008 MSU Alumni Association & Bozeman Area Chamber of Commerce Award for Excellence. (nominated by student recipient Patrick Kujawa).
    • Finalist, Best Paper Award, "Characterization Methodology for High Density Microwave Fixtures", DesignCon-08, Test and Measurement Track, Feb 2008.
    • Cambridge Who's Who Among Executives and Professionals in Education and Research, "Honors Edition", Selected July 2008.


  5. Funded Projects

    6. 8/06-7/07 Agilent Technologies, Inc.
    "Building a High Speed Digital Design Lab at MSU: Equipment Donation"

    10/07-pres Advanced Acoustic Concepts Inc. (AAC)
    "Wireless Telemetry using Digital Beam Forming of Adaptive Antenna Arrays"

    11/07-pres Montana Microfabrication Facility (MMF)
    "User's Grant for Fabrication of a Novel Coaxial Interconnect Structure"

    1/08-pres Sunstone Circuits
    "Sponsorship: High Speed Signaling Effects in PCBs"

    1/08-pres Montana Space Grant Consortium (MSGC)
    "Radiation Hardened Processor for SW Reconfigurable Wireless Communication"

  6. Consulting

    7. 8/06-2/08 Agilent Technologies, Inc
    Design of DDR2/DDR3 Memory Probes for Logic Analyzers and Oscilloscopes

  7. Publications

    1. Thesis / Dissertation

      1. "Design and Implementation of a Fuzzy Logic Voltage Controller for a Synchronous Generator",
        Brock J. LaMeres,
        Senior Design Project, Montana State University, Bozeman, MT,
        December 15, 1998. (PDF) (Slides)

      2. "Characterization of a Printed Circuit Board Via",
        Brock J. LaMeres,
        Master's Thesis, University of Colorado, Colorado Springs, CO,
        May 15, 2001. (PDF) (Slides)

      3. "Novel Design Techniques to Reduce Simultaneous Switching Noise in VLSI Packaging",
        Brock J. LaMeres,
        Ph.D. Thesis, University of Colorado, Boulder, CO,
        December 16, 2005. (PDF) (Slides)

    2. Fully Refereed Journal Articles

      1. "Controlling the Average Residential Electric Water Heater Power Demand Using Fuzzy Logic",
        B.J. LaMeres, M.H. Nehrir, and V. Gerez,
        Journal of Electric Power Systems Research, vol. 52, pp. 267-271,
        February 1999. (PDF)

      2. "Fuzzy Logic Based Voltage Controller for a Synchronous Generator",
        Brock J. LaMeres, M.H. Nehrir,
        IEEE Computer Applications in Power, vol. 12, no. 2, pp. 46-49,
        April 1999. (PDF)

      3. "An Approach to Evaluate the General Performance of Stand-Alone Wind/Photovoltaic Generating Systems",
        M.H. Nehrir, B.J. LaMeres, G. Venkataramanan, V.Gerez, and L.A. Alvarado,
        IEEE Transactions on Energy Conversion, vol 15, no. 4, pp. 433-439,
        December 2000. (PDF)

      4. "A multiple-block fuzzy logic-based electric water heater demand-side management strategy for leveling distribution feeder demand profile",
        M.H. Nehrir, and B.J. LaMeres,
        Journal of Electric Power Systems Research, vol. 56, pp. 225-230,
        March 2000. (PDF)

      5. "Time Domain Analysis of a Printed Circuit Board Via",
        Brock J. LaMeres, T.S. Kalkur,
        Microwave Journal, vol. 43, no. 11, pp. 76-84,
        November 2000. (PDF)

      6. "Effect of Ground Vias on Changing Signal Layers in a Multi-Layered PCB",
        B.J. LaMeres and T.S. Kalkur,
        Microwave and Optical Technology Letters, vol. 28, no. 4, pp. 257-260,
        February 20, 2001. (PDF)

      7. "FPGA I/O - When to go Serial",
        Brock LaMeres,
        IEE Electronic Systems and Software, vol. 2, no. 3, pp. 14-18,
        June 2004. (PDF)

      8. "Novel 3-D Coaxial Interconnect System for use in SiP Applications",
        Brock LaMeres, Christopher McIntosh, and Monther Abusultan
        IEEE Transactions on Advanced Packaging, TADVP-2008-084. Under Review

    3. Fully Refereed Conference Proceedings

      4. These are formal papers that were invited or accepted for presentation at a scholarly conference based on peer review of the entire manuscript.

      1. "Component Sizing for Stand-Alone Wind-Electric Generating Systems: Frequency and Time Span of Data Needed",
        M.H. Nehrir, G. Venkataramanan, V. Gerez, and B. LaMeres,
        Proceedings, 17th Annual ASME Wind Energy Symposium,
        Jan 11-15, 1998, Reno, NV. (PDF)

      2. "Shifting Residential Electric Thermal Storage Loads: An Automated Fuzzy Logic-Based Control Strategy",
        M.H. Nehrir, V. Gerez, and B.J. LaMeres,
        Proceedings, 1998 World Automation Congress, (WAC-98)
        May 10-14, 1998, Anchorage, Alaska. (PDF)

      3. "Controlling the Average Residential Electric Water Heater Power Demand Using Fuzzy Logic",
        B.J. LaMeres, M.H. Nehrir, and V. Gerez,
        Proceedings, 1998 North American Power Symposium,
        Oct 18-20, 1998, Cleveland, Ohio. (PDF)

      4. "A Customer-Interactive Electric Water Heater Demand-Side Management Strategy Using Fuzzy Logic",
        M.H. Nehrir, B.J. LaMeres, and V. Gerez,
        1999 IEEE Power Engineering Society Winter Meeting,
        Jan 31 - Feb 4, 1999, New York, NY. (PDF)

      5. "Performance Evaluation of Stand-Alone Wind/PV Generating Systems",
        M.H. Nehrir, B.J. LaMeres, G. Venkataramanan, V. Gerez, L.A. Alvarado,
        Power Engineering Society Summer Meeting, IEEE, vol. 1, pp. 555-559,
        July 18-22, 1999, Edmonton, Alta, Canada. (PDF)

      6. "Fuzzy logic-based direct load control of residential electric water heaters and ACs recognizing customer preferences in a deregulated environment",
        H. Salehfar, P.J. Noll, B.J. LaMeres, M.H. Nehrir, V. Gerez,
        Power Engineering Society Summer Meeting, IEEE, vol. 2, pp. 1055-1060,
        July 18-22, 1999, Edmonton, Alta, Canada. (PDF)

      7. "A Fuzzy Logic-Based Synchronous Generator Voltage Regulator Optimized with a Genetic Algorithm",
        B.J. LaMeres and M.H. Nehrir,
        Proceedings, 2000 World Automation Congress, (WAC-00)
        June 11-16, 2000, Maui, HI. (PDF)

      8. "Encoding-based Minimization of Inductive X-talk for Off-chip Data Tx",
        B.J. LaMeres and S.P. Khatri,
        Design Automation and Test in Europe (DATE-05),
        March 13, 2005, Munich, Germany. (PDF) (Slides)

      9. "Performance Model for Inter-chip Communication Considering Inductive Cross-talk and Cost",
        B.J. LaMeres and S.P. Khatri,
        IEEE International Symposium on Circuits and Systems (ISCAS-05),
        May 23, 2005, Kobe, Japan. (PDF) (Slides)

      10. "Broadband Impedance Matching for Inductive Interconnect in VLSI Pkg.",
        B.J. LaMeres and S.P. Khatri,
        IEEE International Conference on Computer Design (ICCD-2005),
        October 2, 2005, San Jose, CA. (PDF) (Slides)
        Best Paper Award: Circuit Consideration in Process Design

      11. "Controlling Inductive X-talk and Power in Off-chip Buses using CODECs",
        Brock LaMeres, Kanupriya Gulati, and Sunil Khatri,
        Asia and South Pacific Design Automation Conference (ASP-DAC),
        Jan 24, 2006, Yokohama, Japan. (PDF) (Slides)

      12. "Bus Stuttering : An Encoding Technique to Reduce Inductive Noise in Off-Chip Data Transmission",
        B.J. LaMeres and S.P. Khatri,
        Design Automation and Test in Europe (DATE-06),
        March 10, 2006, Munich, Germany. (PDF) (Slides)

      13. "Controlled Impedance Interconnect Using Coplanar Wire Bond Structures",
        Samuel Harkness, Jeffrey Meirhofer, and Brock J. LaMeres
        IEEE Electrical Performance of Electronic Packaging Conference (EPEP-08)
        Oct 27, 2008, San Jose, CA, Under Review

    4. Refereed Conference Proceedings

      5. These are formal papers that were invited or accepted for presentation at a scholarly conference based on peer review of an abstract or extended summary only.

      1. "Logic Analyzer Probing Techniques for High-Speed Digital Systems",
        Brock J. LaMeres,
        DesignCon 2003 - High Performance Systems Track
        Jan 27, 2003, Santa Clara, CA, (PDF) (Slides)

      2. "High Speed Digital Systems Require Advanced Probing Techniques for Logic Analyzer Debug",
        Brock LaMeres,
        JEDEX San Jose Memory Conference - Memory Futures Track
        March 24, 2003, San Jose, CA. (PDF) (Slides)

      3. "Design of Low-Power Diff Repeater Using Low-Voltage & Charge Recycling",
        B.J. LaMeres and S.P. Khatri,
        DesignCon 2005,
        Feb 2, 2005, Santa Clara, CA. (PDF) (Slides)

      4. "Performance Model for Inter-Chip Busses Considering BW and Cost",
        B.J. LaMeres and S.P. Khatri,
        DesignCon 2005,
        Feb 2, 2005, Santa Clara, CA. (PDF) (Slides)
        Best Paper Award : Board Level Design Track

      5. "Connector-Less Logic Analyzer Probing - Mechanical and Electrical Advantages"
        Brock LaMeres, Brent Holcombe, & George Marshall,
        DesignCon 2005,
        Feb 2, 2005, Santa Clara, CA. (PDF) (Slides)

      6. "Design of Low-Power Diff Repeater Using Low-Voltage & Charge Recycling"
        B.J. LaMeres and S.P. Khatri,
        DesignCon East 2005,
        Sept 22, 2005, Worcester, MA. (PDF) (Slides)

      7. "Performance Model for Inter-Chip Busses Considering Bandwidth & Cost",
        B.J. LaMeres and S.P. Khatri,
        DesignCon East 2005,
        Sept 22, 2005, Worcester, MA. (PDF) (Slides)

      8. "Connector-Less Logic Analyzer Probing - Mechanical and Electrical Advantages"
        Brock LaMeres, Brent Holcombe, & George Marshall,
        DesignCon East 2005,
        Sept 22, 2005, Worcester, MA. (PDF) (Slides)

      9. "Impedance Matching Techniques for VLSI Packaging",
        Brock LaMeres, Kanupriya Gulati, Rajesh Garg, & Sunil Khatri,
        DesignCon 2006,
        Feb 6, 2006, Santa Clara, CA. (PDF) (Slides)

      10. "Off-Chip Coaxial to Microstrip Transition Using MEMS Trench",
        Brock J. LaMeres and Chris McIntosh,
        13th NASA Symposium on VLSI Design,
        June 5, 2007, Post Falls, ID. (PDF) (Slides)

      11. "Characterization Methodology for High Density Microwave Fixtures",
        Brock J. LaMeres, Brent Holcombe, and Emad Soubh
        DesignCon 2008,
        February 4, 2008, Santa Clara, CA. (PDF) (Slides)
        Best Paper Award Finalist: Test and Measurement Track

      12. "Off-Chip Coaxial to Coplanar Transition Using a MEMS Trench",
        Monther Abusultan and Brock J. LaMeres
        3D/SiP Advanced Packaging Symposium,
        April 28, 2008, Durham, NC. (PDF) (Slides)

      13. "Fab Process For High Speed Coaxial To Coplanar Off-Chip Interconnect",
        Christopher McIntosh and Brock J. LaMeres
        Electronics Systems-Integration Technology Conference (ESTC 2008),
        Sept 1-4, 2008, Greenwhich, London, UK. Accepted for Publication

      14. "A Power-Efficient Design Approach to Radiation Hardened Digital Circuitry using Dynamically Selectable Triple Modulo Redundancy",
        Brock J. LaMeres & Clinton Guaer
        Military and Aerospace Programmable Logic Devices (MAPLD) Conference,
        Sept 15, 2008, Annapolis, MD. Accepted for Publication

      15. "Dynamic Reconfigurable Computing Architecture for Aerospace Apps.",
        Brock J. LaMeres & Clinton Guaer
        2009 IEEE Aerospace Conference,
        Mar 7-14, 2009, Big Sky, MT. Accepted for Publication

      16. "Electrical Characterization of a Novel Coaxial Die-to-Die Interconnect",
        Christopher McIntosh, Samuel Harkness, and Brock J. LaMeres
        2009 IEEE Aerospace Conference,
        Mar 7-14, 2009, Big Sky, MT. Accepted for Publication

    5. Non-Refereed Publications / Trade Journals

      1. "FPGA Logic Analysis",
        Brock J. LaMeres, Printed Circuit Design, pp 21-24, July 2002. (PDF)
        Brock J. LaMeres, Elektro Automation, July 2002. (PDF)

      2. "Choosing a High-Speed Logic Analyzer Probe",
        Brock LaMeres, Electronic Products", November 2003. (PDF)

      3. "Logic Analyzer Connectorless Probing Reduces Loading and Footprint Impact on DDR Memory Validation",
        Brock LaMeres, TechOnLine, March 2004. (PDF)
        Brock LaMeres, Micro Electronics Japan, June 2004. (PDF)

      4. "Your Logic Analyzer Can Probe those Forgotten Signals",
        B. LaMeres & K. Johnson, EE Product Center, May 2004. (PDF)
        B. LaMeres & K. Johnson, Planet Analog, June 8, 2004. (PDF)
        B. LaMeres & K. Johnson, Component Times, May 2004. (PDF)
        B. LaMeres & K. Johnson, Wall Street & Technology, May 2004. (PDF)
        B. LaMeres & K. Johnson, Bank Systems & Technology, May 2004. (PDF)

      5. "Differential Logic Analyzer Probing",
        Brock LaMeres, AnalogZone, June 2004. (PDF)
        Brock LaMeres, Mesures (in German), July 2005. (PDF)

      6. "Physical Connections are Key in FPGA Debug",
        Brock LaMeres, COTS Journal, June 2004. (PDF)

      7. "Taking Logic-Analyzer Probing For Granted Can Spell Trouble",
        B. LaMeres & K. Johnson, Electronic Design, August 2004. (PDF)
        B. LaMeres & K. Johnson, Electronic Products China, July 2004. (PDF)

      8. "Connectorless Probes Simplify Digital Design",
        LaMeres & Holcombe, Electronic Engineering Times Asia, Aug 2004. (PDF)

      9. "FPGA I/O - When to go Serial",
        Brock LaMeres,
        FPGA and Programmable Logic Journal, August 2004. (PDF)

      10. "How Much Bandwidth Does Your Logic Analyzer Need",
        Brock LaMeres, TechOnLine, November 2004. (PDF)

      11. "When to Make the Move to Advanced Probing Technology in Logic Analysis",
        Brock LaMeres, RF Design, July 2005. (PDF)

      12. "Connectorless Probing Enables HyperTransport Debug at 2.4Gb/s",
        Brock LaMeres, TechOnline (www.techonline.com), October 2005. (PDF)
        Brock LaMeres, Nuevos Retos En Interconexiones, February 2006. (PDF)

      13. "Compression Probe Technology Makes Sense in Logic Analyzers",
        B. LaMeres & B. Holcombe, Connector Specifier Magazine, June 2006. (PDF)


  8. Invited Talks

    1. "RF Effects in PCB Design",
      Brock LaMeres,
      IEEE Pikes Peak Technology Conference (TechCon-01), Colorado Springs, CO. April 2001. (PDF)

    2. "Challenges in Debugging at 5GHz",
      Brock LaMeres, John Calvin, & Sarah Boen
      Intel's Developers Forum (IDF-Fall-05), San Francisco, CA. August 23, 2005. (PDF)

    3. "Compensation for Simultaneous Switching Noise in VLSI Packaging",
      Brock LaMeres,
      MCEN 5166 - Electronic Packaging Class, University of Colorado, Boulder. September 15, 2005. (PDF)

  9. Patents

    1. "Alignment/Retention Device for Connector-Less Probe",
      Brent A. Holcombe & Brock J. LaMeres
      US Patent 6,822,466, November 23, 2004. (PDF)

    2. "Electronic Probe Extender",
      Brock J. LaMeres & Kenneth W. Johnson
      US Patent 7,025,628, April 11, 2006. (PDF)

    3. "Probes with perpendicularly disposed spring pins, and methods of making and using same",
      Brock J. LaMeres, Brent A. Holcombe, & Kenneth Johnson
      US Patent 7,046,020, May 16, 2006. (PDF)

    4. "Probe assembly with controlled impedance spring pin or resistor tip spring pin contacts",
      Brent A. Holcombe, Brock J. LaMeres, & Donald M. Logelin
      US Patent 7,116,121, October 3, 2006. (PDF)

    5. "Apparatus, method, and kit for probing a pattern of points on a printed circuit board",
      Brock J. LaMeres, Brent A. Holcombe, & Kenneth Johnson
      US Patent 7,145,352, December 5, 2006. (PDF)

    6. "Incorporation of isolation resistor(s) into probes using probe tip spring pins",
      Brock J. LaMeres, Brent A. Holcombe, & Glenn Wood
      US Patent 7,183,781, February 27, 2007. (PDF)

    7. "Signal Probe and Probe Assembly",
      Joseph Groshong, Brock J. LaMeres, & Brent A. Holcombe
      US Patent 7,242,202, July 10, 2007. (PDF)

    8. "Probe Retention Kit, and System and Method for Probing a Pattern of Points of a PCB",
      Brock J. LaMeres, Brent A. Holcombe, & Kenneth Johnson
      US Patent 7,242,203, July 10, 2007. (PDF)

    9. "Regenerator Probe",
      Glenn Wood, Donald M. Logelin, Brock J. LaMeres, & Brent A. Holcombe
      US Patent 7,282,935, Oct 16, 2007. (PDF)

    10. "Probe having a frame to align spring pins perpendicularly to a printed circuit board, and method of making same",
      Brock J. LaMeres & Brent A. Holcombe
      US Patent 7,323,892, Jan 29, 2008. (PDF)

    11. "Board-to-Board Electronic Interface Using Hemi-Ellipsoidal Surface Features",
      Kenneth Johnson & Brock J. LaMeres
      US Patent 7,338,292, Mar 4, 2008. (PDF)

    12. "Method and apparatus for probing at arbitrary locations within an inaccessible array of leads the solder balls or pins actually connecting a VLSI IC package to a substrate or socket",
      Brent Holcombe, Brock J. LaMeres, & Kenneth Johnson
      US Patent 7,372,284, May 13, 2008. (PDF)


  10. Service

    1. Montana State University, Bozeman, MT.

      2. • College of Engineering, Faculty Development Committee 4/07-present
      • ECE Department, Promotion & Tenure Committee 8/07-present
      • ECE Department, Undergraduate Curriculum Committee 8/07-present
      • IEEE Student Chapter Advisor 8/07-present

    2. Professional Committees & Staff

      3. • Technical Program Committee, DesignCon 04,07,08,09
      • Editorial Staff, "Active & Passive Electrical Components Journal" 9/06-present

    3. Conference Paper Reviews

      4. • DesignCon 04,07,08,09
      • International Conference on Circuits & Systems (ISCAS) 2008
      • ASME International Mechanical Engineering Congress & Expo 2008

    4. Book Reviews

      5. • R. Dubey, "Programmable Logic for Motor Control", Springer Pub. 2006
      • H.W. Huang, "Emb. Sys. Design with C8051", Wiley & Sons Pub. 2007

    5. Hosted Talks

      6. • Jason Kracht, Agilent, "Spectrum Analyzers", IEEE Sect. Meet 4/07


  11. Student Advising & Supervision

    1. Graduate Student Research (EE590-Thesis, Primary Advisor)

      2. • Srinitha Nimmakayala MSEE Radiation Hardened SRAM 2006-present
      • Christopher McIntosh MSEE Fab of Novel MEMS Interconnect 2007-present
      • Charles Ostrander MSEE FPGA HW for Spectral Imaging 2007-present
      • Monther Abusultan MSEE Digital Beam Forming HW 2008-present
      • Clint Guaer MSEE Radiation Hardened Computing 2008-present

    2. Graduate Committees (Member)

      3. • Dwayne Folden MSEE SW Interface for Antenna Testbed 2006-2007
      • Chris Davenport MSEE Parallel Processing Techniques 2006-2008
      • Dustin Foran MSEE WiMax Preamble Decoding 2006-2008
      • Justin Hadella MSEE Software Defined Cognitive Radio 2007-present
      • Heather Moreland PhD,Mth Graduate Representative 2008-present

    3. Graduate Student Research (EE570-Ind. Study)

      4. • Srinitha Nimmakayala MSEE Programmable Termination (2cr) Fall-2006
      • Monther Abusultan MSEE Xtalk on Coplanar/Coax Lines (1cr) Sum-2008

    4. Undergraduate Student Research (Hourly)

      5. • Andy Meehan BSEE FPGA Phase Detector 2007
      • Monther Abusultan* BSCpE FEA of Package Interconnect 2007-2008
      • Ray Weber BSCpE Adaptive Array Testbed 2007-2008

      * this work resulted in the awarding of an undergraduate scholars (USP) fellowship.

    5. Undergraduate Student Research (EE490-Thesis)

      6. • Orion Bukantis BSEE WiMAX Simulink Model (3cr) Spring-2008
      • Ryan Cyr BSCpE Laser Temp Controller (3cr) Spring-2008

    6. Research Experience for Undergraduate Students (NSF REU)

      7. • Lex Movius ASCpT Digital Beam Forming Sum-2007
      • Sam Harkness BSEE Package Interconnect Modeling Sum-2008
      • Jeff Meirhofer BSEE Frequency Dependant T-Line Loss Sum-2008

    7. Senior Design Projects Sponsored or Supervised (Capstone)

      8. • Erik Smith BSEE FPGA-based PID Controller 2006-2007
      • Kelli Grabbe BSEE FPGA-based PID Controller 2006-2007
      • Susie Regan BSEE FPGA-based PID Controller 2006-2007
      • Ryan Cyr BSCpE Laser Diode Temperature Controller 2007-2008
      • Clint Guaer BSCpE Laser Diode Temperature Controller 2007-2008
      • Andy Mahlen BSEE Laser Diode Temperature Controller 2007-2008

    8. Undergraduate Advising

      9. I currently serve as the primary advisor for 34 undergraduate students in the ECE department.

  12. Professional Registration

    • Registered Professional Engineer, Colorado, Reg # 37255, (12/30/02 - present).
    • Registered Professional Engineer, Montana, Reg # 13627, (11/8/06 - present).


  13. Professional Membership

    • IEEE, Member, (1998-present).
    • IEEE Computer Society, Member, (2006-present)
    • IEEE Components, Packaging, and Manufacturing Technology Society - CPMT, Member, (2006-present)


  14. Honorary Membership

    • Eta Kappa Nu, Electrical Engineering Honor Society, Montana State University, Bozeman, 1997. (President, 1998)
    • Tau Beta Pi, Engineering Honor Society, Montana State University, Bozeman, 1997.
    • Phi Kappa Phi, National Honor Society, Montana State University, Bozeman, 1997.
    • Golden Key, National Honor Society, Montana State University, Bozeman, 1997.




View Text-only Version Text-only Updated: 12/1/2007
spacer
spacer
© Montana State University 2006 Didn't Find it? Please use our contact list or our site index.