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> College of Engineering > Electrical & Computer Engineering Department
LaMeres' Research
High Speed Digital Design
High-speed digital design is the generation and transmission of digital signals at a high enough frequency that the analog properties of the circuitry and interconnect must be considered. This paradigm shift in the way digital logic is approached is fueled by the dramatic improvement in integrated circuit fabrication technology. As device feature sizes continue to shrink, the speed at which digital signals can be generated is increased. As frequencies rise, the distributed nature of the materials that are used to fabricate the devices and interconnect must be approached differently. Analog circuit theory must be adapted to the generation of digital signals. Microwave circuit theory must be adapted to the design of interconnect systems. In addition, new physical structures must be invented that can generate and transmit the high-speed digital signals to meet the computation demands of the next decade.
The continual improvement in the on-chip fabrication technology has also created paradigm shifts in the way digital logic is implemented. Programmable logic has benefited from improvements made in device fabrication. Field Programmable Gate Arrays (FPGA's) are beginning to compete with the once superior Application Specific Integrated Circuits (ASICs). The flexibility in a programmable element is fueling the need for more advanced programmable cells and novel partitioning algorithms that can combine ASIC and programmable circuitry to create a more efficient and higher performing computational block.
The MSU High Speed Digital Design Laboratory (HDSSL) is committed to researching technology that will aid in the continued improvement of digital signal generation and transmission. The lab is also focused on improving the programmable logic cell and exploring efficient partitioning between ASIC and programmable logic circuitry. Students working in the HSDDL are exposed to future looking research (5+ years) in addition to shorter term projects sponsored by industrial partners such as Agilent Technologies and Xilinx. Work within the HSDDL includes :
- Interconnect & Packaging
- High Frequency Digital Circuit Design
- Programmable Logic / FPGA's
Interconnect & Packaging
All digital signals need to traverse some type of interconnect, whether it be on-chip traces, IC packaging, printed circuit boards, cables, or connectors. With the exponential increase in on-chip device fabrication capability, edge rates from digital drivers will drop below 10ps within the next decade. These edge rates will require interconnect systems with up to 100 GHz of bandwidth to exist. Traditional interconnect and manufacturing processes will not be capable of meeting this demand. New styles of interconnect and design philosophies must be invented to keep pace with the ever increasing device technology. Microwave design principles will need to be adapted to meet these challenges. The engineer of tomorrow will no longer talk of interconnect in terms of lumped RC delay, but rather in terms of distributed parasitics, group delay, skin effect, and dielectric loss.
Resources on Interconnect & Packaging:
High Frequency Digital Circuit Design
Generating digital signals for the transmission of data is becoming an analog design task. Digital circuits no longer be thought of in terms of delay, power, and area. Tomorrow's digital circuits must consider the analog properties of the waveshape and the distributed nature of the materials that are used to fabricate the devices.
Resources on High Frequency Digital Circuit Design:
Programmable Logic
Reconfigurable digital circuitry has always provided inherent design flexibility. Historically, this flexibility has come at the expense of performance. However, with advances in IC fabrication technology, programmable logic performance has advanced to the point where it is beginning to meet the computation needs of modern applications. This has created a paradigm shift in the way digital circuitry can be implemented. If programmable logic cells can perform as well as structured ASIC blocks, then the standard VLSI design flow will need to be reinvented. With multiple logic functions being able to be implemented within the same programmable logic cell, standard approaches to computer architecture and logic partitioning will not apply. New computer architectures based on programmable logic cells are needed to exploit the advantages of programmable circuits. In addition, partitioning algorithms which combine ASIC and programmable logic cells need to be created. Finally, improving the performance, power consumption, and area impact of the standard programmable block must be addressed.
Resources on Programmable Logic:
Current Projects
- Broadband Impedance Compensator - IC Design & Fabrication
- "No Contact" Logic Probe - Interconnect & Amplifier Design & Fabrication
- Next Gen Programmable Logic Block - Investigation into advanced techniques for programmable logic cells
- Programmable Fuel Cell Controller - General Purpose, FPGA-based, Real Time Control Platform
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