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Academics
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Administration
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Admissions
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A-Z Index
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Directories
Course Description
Schedule
Information
Grades
Contact Us
Course Staff
Instructor
Dr. Brock J. LaMeres
533 Cobleigh Hall
Bozeman, MT 59717
Tel: (406) 994-5987
Fax: (406) 994-5958
lameres@ece.montana.edu
Teaching Assistant
Clint Gauer
601 Cobleigh Hall
Bozeman, MT 59717
clint.gauer@myportal
EE 367 - Logic Design
(Spring 2008)
Course Information
Course Documents
Course Syllabus
Homework Information
HW #2 Downloads:
Evita VHDL Tutorial
: self extracting zip file (3.4M)
HW #3 Downloads:
inv1.vhd
HW #3 Downloads:
test_logic_gates.vhd
HW #3 Downloads:
hw_02_visio_template.vsd
HW #4 Downloads:
test_decoder_3to8.vhd
HW #5 Downloads:
test_decoder_3to8.vhd
HW #6 Downloads:
test_alu.vhd
HW #9 Downloads:
test_alu.vhd
HW #10 Downloads:
test_adder.vhd
HW #11 Downloads:
AnalogDevices_ADC_AD7478A.pdf
HW #11 Downloads:
ADC_AD7478A.vhd
HW #11 Downloads:
test_ADC_controller.vhd
Lab Information
Lab #1 Downloads:
top.vhd
Lab #1 Downloads:
counter.vhd
Lab #1 Downloads:
clock_div.vhd
Lab #1 Downloads:
test_top.vhd
Lab #3 Downloads:
test_top.vhd
Lab #3 Downloads:
top.vhd
Lab #3 Downloads:
counter.vhd
Lab #3 Downloads:
clock_div.vhd
Lab #3 Downloads:
lcd_blkbx.vhd
Lab #3 Downloads:
lcd_counter.vhd
Lab #3 Downloads:
lcd_clock_div.vhd
Lab #5 Downloads:
lcd_driver.vhd
Lab #5 Downloads:
lcd_counter.vhd
Lab #5 Downloads:
lcd_clock_div.vhd
Lab #4 Downloads:
unisim_VCOMP.vhd
- For Reference Only, this is already included in Xilinx ISE
Lab #6 Downloads:
test_top.vhd
Lab #7 Downloads:
test_top.vhd
Lab #8 Downloads:
test_top.vhd
Lab #9 Downloads:
test_top.vhd
Lab #10 Downloads:
lab_10_microcomputer.zip
VHDL Information
MSU VHDL Guide
by Dr. Fred Cady (19k)
The VHDL Cookbook
by Peter J. Ashenden (299k)
"VHDL Starts Guide" by Sudhakar Yalamanchili
Chapter 1 - Introduction
(426k)
Chapter 2 - Simulation of Digital Systems
(381k)
Chapter 3 - Basic Language Concepts
(392k)
Chapter 4 - Modeling Behavior
(473k)
Chapter 5 - Modeling Structure
(388k)
Chapter 6 - Subprograms, Packages, and Libraries
(389k)
Chapter 7 - Basic Input/Output
(354k)
Chapter 8 - Programming Mechanics
(218k)
Chapter 9 - Identifiers, Data Types, and Operators
(223k)
STANDARD
from Synopsys (69k)
STD_LOGIC_1164
from Synopsys (69k)
STD_LOGIC_ARITH Package
from Synopsys (69k)
STD_LOGIC_UNSIGNED Package
from Synopsys (12k)
STD_LOGIC_SIGNED Package
from Synopsys (5k)
Mentor Graphics ModelSim Information:
ModelSim User's Guide
(4.1M)
ModelSim Tutorial
(1M)
Xilinx Eval Board Information:
Xilinx ML403 User's Guide
(590k)
Xilinx ML403 Getting Started
(795k)
Xilinx ML403 EDP Processor Reference Design User Guide
(892k)
Xilinx ML403 Schematics
(984k)
Xilinx ML403 Gerber Plots
(6M)
Xilinx ML403 Fab Drawing
(208k)
Xilinx ML403 Product Brief
(278k)
LCD Datasheet
(728k)
Xilinx ISE Information:
Xilinx ISE 8 In Depth Tutorial
(2M)
Xilinx ISE 8 Quick Start Tutorial
(665k)
Misc:
Programmer's File Editor
(597k, just unzip and run)
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Updated: 1/16/2008
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