Montana State University

Department of Electrical and Computer Engineering

EE317 -- Electronics

 Fall 2008

 

Class is Monday, Wednesday, Friday 9:00-9:50 in Roberts 218.

Labs meet on Tuesdays, 12:10-2:00, 2:10-4:00 and 4:10-6:00 in Cobleigh 621.

The professor this term is David Dickensheets, davidd@ee.montana.edu, (406) 994-7874, 530 Cobleigh Hall.

David's Office Hours are MWF 10:00-11:00, Tu. 2:00-3:00, W 4:00-5:00.

The TA this term is Ningkonsin Rajkumar, ningkon@rediffmail.com, (406) 994-4271, 636 Cobleigh Hall.

Ningkonsin's Office Hours are Mon, Wed, Fri from 10:30 to 11:30

 

Announcements

Exams

2008 midterm#2  solutions: pg2 pg3 pg4 pg5 pg6 pg7

2008 midterm#1  solutions: pg2 pg3 pg4 pg5

Handouts

2.      hard clipped

3.      cross-over distortion With extreme crossover distortion (at 0.1 of max amplitude)

 

Lectures

Diode Small Signal Model

Intro to BJTs

Reading Assignments

To be completed prior to lecture on the indicated dates

Lecture Date

Reading Assignment

Lecture Topic

9/3

Intro to course; Thevenin/Norton review

9/5

Sedra sections 1.1-1.6; 3.1

Amplifier models; diode intro; ideal diode

9/8

Sedra section 3.2

Ideal diode circuit examples; p-n junction characteristics

9/10

Sedra section 3.3

Large signal diode model; rectifier example

9/12

Sedra section 3.3, (3.4, 3.5)

Small signal diode model; diode switch example; diode attenuator example

9/15

Sedra section 3.4, 3.5, 3.6

Zener diodes; zener models

9/17

Sedra section 3.7

Design problem discussion; Diode p-n junction physics

9/19

Sedra section 3.7

Diode p-n junction physics

9/22

Sedra section 3.7

Diode p-n junction physics

9/22

Sedra section 3.8,3.9

p-n physics wrap-up; Pspice simulation of diodes

9/24

Sedra section 4.1

FET device structure and physical operation; i-v characteristics

9/26

Sedra section 4.2&4.3

FET large signal model; p-channel; DC bias

9/29

Sedra section 4.3,4.5

FET DC bias 

10/1

Sedra section 4.4,4.6

FET small signal model and FET amplifier circuits

10/3

Sedra section 4.6

FET amplifier circuits

10/6

Sedra section 4.7

FET CS and CD amplifier intro

10/8

Sedra section 4.7, 4.5

FET CS and CD amplifier

10/10

Midterm 1

10/13

Sedra section 4.7

FET CG amplifier

10/15

Sedra section 4.5.4 and 6.3, 6.5

Active biasing, active load CS amplifier

10/17

Sedra section 4.8,1.6

MOSFET capacitances and high frequency model

10/20

Sedra section 1.6, 4.9

Frequency response review (Bode), Amplifier frequency response

10/22

Sedra section 4.10

CMOS logic concepts - inverter

10/24

Sedra section 4.10

CMOS inverter wrapup - inverter design problem

10/27

Sedra section 4.11,4.12

Inverter propagation delay, fan out limits; MOS switches

10/29

MOS SPICE models; Intro to Bipolar Junction Transistors

10/31

Sedra section 5.1

BJT device physics

11/3

Sedra section 5.1,5.2,5.3

BJT Large signal circuit models and terminal characteristics

11/5

Sedra section 5.2,5.5

PNP devices; BJT DC analysis

11/7

Sedra section 5.4,5.5

BJT DC analysis

11/10

Sedra section 5.3,5.6

small signal amplifier 

11/12

Sedra section 5.3,5.6

small signal amplifier continued

11/14

Sedra section 5.6, 5.7

small signal analysis of single stage amplifiers

11/17

midterm #2

Covers: FETs (amplifiers, active bias/load, frequency response, CMOS inverter, MOS switch) BJTs (terminal characteristics and large signal model, DC bias analysis)

11/19

small signal analysis wrapup

11/21

Sedra 5.8, 5.9

high frequency model of BJT, freq. response

11/24

Sedra 5.9

freq. response

11/26

Sedra 5.10

saturation, cutoff and digital applications

12/1

Sedra 2.1-2.8

op-amps and practical design

12/3

Sedra 2.1-2.8

op-amps and practical design continued

12/5

Sedra 14.1-14.4

power output stages - class A, class AB, class B

12/8

Sedra 14.1-14.4

power output stages wrap-up, review

12/10

12/12

Final Review

Problem Sets

set #

Due Date

Problems

Solutions                   

1

9/5

PRETEST

 

2

9/8

current amplifier

current amplifier

3

9/10

3.9, 3.11

3.9, 3.11

4

9/12

3.20, 3.26

3.20, 3.26

5

9/17

3.49, 3.54, 3.97

3.49, 3.54, 3.97

6

9/19

zener regulator, 3.83

3.83a, 3.83b, zenreg

7

9/22

3.112, 3.115

3.112&3.115a, 3.115b

8

10/6

Regulator Design Problem

 

9

9/26

4.4, 4.7

4.4, 4.7

10

9/29

4.12, 4.15, 4.26

4.12, 4.15, 4.26a, 4.26b

11

10/1

4.35, 4.37, 4.39

4.35, 4.37, 4.39

12

10/3

4.55, 4.65

4.55, 4.65

13

10/8

4.68, 4.69, 4.74

4.68, 4.69, 4.74

14

10/15

4.81, 4.82, 4.85

4.81, 4.82, 4.85

15

10/20

active bias problems

current mirror, amp pg1, amp pg2

16

10/22

4.91, 4.92

4.91, 4.92

17

10/24

4.95, 4.99

4.95a, 4.95b, 4.99

18

10/27

4.105, 4.111, 4.112

4.105, 4.111, 4.112

19

10/29

4.116, 4.118

4.116, 4.118

20

11/3

5.3, 5.7, 5.12

5.3, 5.7, 5.12

21

11/5

CMOS Design Problem

 

22

11/7

5.16, 5.20, 5.21

5.16, 5.20, 5.21

23

11/10

5.30, 5.38, 5.46

5.30, 5.38, 5.46

24

11/12

5.55, 5.62, 5.70

5.55, 5.62, 5.70

25

11/14

5.74, 5.85, 5.90

5.74, 5.85a, 5.85b, 5.90

26

11/19

5.108, 5.112, 5.115

5.108, 5.112, 5.115

27

11/21

5.130, 5.137, 5.144

5.130, 5.137, 5.144pg1, 5.144pg2

28

11/24

5.153, 5.157, 5.160, 5.163

5.153, 5.157pg1, 5.157pg2, 5.160, 5.163pg1, 5.163pg2

29

12/1

5.168, 5.170

 5.168, 5.170

30

12/8

op-amp problems

 lpfilt, blopamppg1 blopamppg2; dcoff; logamp1 logamp2 zenerrefpg1 zenerrefpg2 currentsinkpg1 currentsinkpg2

31

12/5

Design Problem

 

(* asterisk indicates design problem)

 

Laboratory

o    Lab 5 10/7 Enhancement MOSFET Biasing (PDF)

o    Lab 6 10/14 Enhancement MOSFET Amplifiers (PDF)

§  Lab Report #2 Due at 5:00 pm Monday 10/20

o    Lab 7 10/21 CMOS Circuits (PDF)

o    Lab 8 10/28 Intro to BJTs (PDF)

o    Lab 9 11/18 BJT amplifiers (PDF)

§  Lab Report #3 Due at 5:00 pm Monday, 11/24

o    Lab 10 11/25 BJT Common Base Amplifier and Logic Inverter (PDF)

o    Lab 11 12/2 BJT Design Problem*

§  Lab Report #4 Due at 5:00 pm Monday, 12/8

 

 

opamps: LM741(National)    LM741(Fairchild)    OP27  OP37  AD8045

diodes: 1N4148    1N4001/2/3/4    1N4733 (5.1V Zener)

transistors: 2N7000 (n channel MOSFET)

2N4124 (npn transistor similar to 2N3904)    2N4126 (npn transistor similar to 2N3906)    BD249 (NPN Power Transistor)

CD4007 (CMOS transistor array, TI datasheet; the Fairchild datasheet is here )

2N4124 (npn transistor similar to 2N3904)    2N4126 (npn transistor similar to 2N3906)


(* asterisk indicates lab activity in which students are building circuits of their own design)

Links

This page is maintained by David Dickensheets.