Montana State University

Department of Electrical and Computer Engineering

EE317 -- Electronics

 Fall 2009

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Class is Monday, Wednesday, Friday 9:00-9:50 in Roberts 218.

Labs meet on Tuesdays, 12:10-2:00, 2:10-4:00 and 4:10-6:00 in Cobleigh 621.

The professor this term is David Dickensheets, davidd@ee.montana.edu, (406) 994-7874, 530 Cobleigh Hall.

David's Office Hours are MW 3:30-5:00, Tu. 9:30-10:30, F 1:30-3:00.

The TA this term is Ningkonsin Rajkumar, ningkon@gmail.com , cell# (408) 204-2810, 528 Cobleigh Hall.

Ningkonsin's Office Hours are W 3-5, F 3-4

The grader this term is Adel Nehmeh, adel.nehmeh@msu.montana.edu, 994-5975, 638 Cobleigh Hall

Adel is often available MWF 12:30-1:00, but emailing for an appointment is the best way to arrange a time to meet with him..

Announcements

Midterm #2 is Friday, Nov. 20

2008 Midterm #2 (pdf); solution pg2 pg3 pg4 pg5 pg6 pg7

2009 Midterm #1 Solutions: pg2 pg3 pg4 pg5, histogram avg: 79, stdev: 14, max: 100, min: 48

Handouts

• Course syllabus (PDF)
• Bode Plot Handout (PDF)
• Bode Plot Demos (view with slide viewer in full-screen mode - click your way through the plots)
• Design Problem Grade Sheet (PDF)
• m-file to iteratively solve for Kn, Vt, n for lab 4: fetfit.m

Reading Assignments

To be completed prior to lecture on the indicated dates

Lecture Date	Reading Assignment	Lecture Topic
8/31		Intro to course; Thevenin/Norton review
9/2	Sedra sections 1.1-1.6; 3.1	Amplifier models; diode intro; ideal diode
9/4	Sedra section 3.2	Ideal diode circuit examples; p-n junction characteristics
9/9	Sedra section 3.3	Large signal diode model; rectifier example
9/11	Sedra section 3.3, (3.4, 3.5)	Small signal diode model; diode switch example; diode attenuator example
9/14	Sedra section 3.4, 3.5, 3.6	Zener diodes; zener models
9/16	Sedra section 3.7	Design problem discussion; Diode p-n junction physics
9/18	Sedra section 3.7	Diode p-n junction physics
9/21	Sedra section 3.7	Diode p-n junction physics
9/23	Sedra section 3.8,3.9	p-n physics wrap-up; Pspice simulation of diodes
9/25	Sedra section 4.1	FET device structure and physical operation; i-v characteristics
9/28	Sedra section 4.2&4.3	FET large signal model; p-channel; DC bias
9/30	Sedra section 4.3,4.5	FET DC bias
10/2	Sedra section 4.4,4.6	FET small signal model and FET amplifier circuits
10/5	Sedra section 4.6	FET amplifier circuits
10/7	Sedra section 4.7	FET CS and CD amplifier intro
10/9	Sedra section 4.7, 4.5	FET CS and CD amplifier
10/12	Sedra section 4.7	FET CG amplifier
10/14	Midterm 1	Covers: amplifier models, diodes, diode circuits, FET devices including terminal characteristics in triode and saturation regions and DC bias problems
10/16	Sedra section 4.5.4 and 6.3, 6.5	Active biasing, active load CS amplifier
10/19	Sedra section 4.8,1.6	MOSFET capacitances and high frequency model
10/21	Sedra section 1.6, 4.9	Frequency response review (Bode), Amplifier frequency response
10/23	Sedra section 4.10	CMOS logic concepts - inverter
10/26	Sedra section 4.10	CMOS inverter wrapup - inverter design problem
10/28	Sedra section 4.11,4.12	Inverter propagation delay, fan out limits; MOS switches
10/30		MOS SPICE models; Intro to Bipolar Junction Transistors
11/2	Sedra section 5.1	BJT device physics
11/4	Sedra section 5.1,5.2,5.3	BJT Large signal circuit models and terminal characteristics
11/6	Sedra section 5.2,5.5	PNP devices; BJT DC analysis
11/9	Sedra section 5.4,5.5	BJT DC analysis
11/13	Sedra section 5.3,5.6	small signal amplifier
11/16	Sedra section 5.3,5.6	small signal amplifier continued
11/18	Sedra section 5.6, 5.7	small signal analysis of single stage amplifiers
11/20	midterm #2	Covers: FETs (amplifiers, active bias/load, frequency response, CMOS inverter, MOS switch) BJTs (terminal characteristics and large signal model, DC bias analysis)
11/23	Sedra 5.8, 5.9	high frequency model of BJT, freq. response
11/30	Sedra 5.9	freq. response
12/2	Sedra 5.10	saturation, cutoff and digital applications
12/4	Sedra 2.1-2.8	op-amps and practical design
12/7	Sedra 2.1-2.8	op-amps and practical design continued
12/9	Sedra 14.1-14.4	power output stages - class A, class AB, class B
12/11	Sedra 14.1-14.4	power output stages wrap-up, review

Problem Sets

set #	Due Date	Problems	Solutions
1	9/2	PRETEST
2	9/9	current amplifier	current amplifier
3	9/11	3.9, 3.11	3.9, 3.11
4	9/14	3.20, 3.26	3.20, 3.26
5	9/16	3.49, 3.54, 3.83	3.49, 3.54, 3.83a, 3.83b
6	9/18	zener regulator, 3.97	3.97, zenreg
7	9/21	3.112, 3.115	3.112&3.115a, 3.115b
8	10/5	Regulator Design Problem
9	9/25	4.4, 4.7	4.4, 4.7
10	9/28	4.12, 4.15, 4.26	4.12, 4.15, 4.26a, 4.26b
11	9/30	4.35, 4.37, 4.39	4.35, 4.37, 4.39
12	10/2	4.55, 4.65	4.55, 4.65
13	10/7	4.68, 4.69, 4.74	4.68, 4.69, 4.74
14	10/12	4.81, 4.82, 4.85	4.81, 4.82, 4.85
15	10/19	active bias problems	current mirror, amp pg1, amp pg2
16	10/21	4.91, 4.92	4.91, 4.92
17	10/23	4.95, 4.99	4.95a, 4.95b, 4.99
18	10/28	4.105, 4.111, 4.112	4.105, 4.111, 4.112
19	10/30	4.116, 4.118	4.116, 4.118
20	11/2	5.3, 5.7, 5.12	5.3, 5.7, 5.12
21	11/4	CMOS Design Problem
22	11/6	5.16, 5.20, 5.21	5.16, 5.20, 5.21
23	11/9	5.30, 5.38, 5.46	5.30, 5.38, 5.46
24	11/13	5.55, 5.62, 5.70	5.55, 5.62, 5.70
25	11/16	5.74, 5.85, 5.90	5.74, 5.85a, 5.85b, 5.90
26	11/18	5.108, 5.112, 5.115	5.108, 5.112, 5.115
27	11/23	5.130, 5.137, 5.144	5.130, 5.137, 5.144pg1, 5.144pg2
28	11/30	5.153, 5.157, 5.160, 5.163	5.153, 5.157pg1, 5.157pg2, 5.160, 5.163pg1, 5.163pg2
29	12/2	5.168, 5.170	5.168, 5.170
30	12/4	Design Problem
31	12/7	op-amp problems	lpfilt, blopamppg1 blopamppg2; dcoff; logamp1 logamp2 zenerrefpg1 zenerrefpg2 currentsinkpg1 currentsinkpg2

(* asterisk indicates design problem)

Laboratory

• Lab information
• Notebook guidelines (PDF)
• Notebook grade sheet (PDF)
• Lab report guidelines (PDF)
• Lab report grade sheet (PDF)
• EE317 Lab Parts Kit Inventory (PDF)
• Labs
• Lab 1 9/8 Diode Basics (PDF)
• Lab 2 9/15 Diode Rectifiers and Switches (PDF)
• Lab Notebooks handed in for grading by 5:00 pm Wednesday 9/16
• Lab 3 9/22 PSpice Analysis of Diode Circuits (PDF)
• Lab Report #1 Due at 5:00 pm Monday 9/28
• Lab 4 9/29 Diode Design Problem (PDF)*
• Lab 5 10/6 Enhancement MOSFET Biasing (PDF)
• Lab 6 10/13 Enhancement MOSFET Amplifiers (PDF)

• Lab Report #2 Due at 5:00 pm Monday 10/19

• Lab 7 10/27 CMOS Circuits (PDF)

• Lab 8 11/10 Intro to BJTs (PDF)
  

• Lab 9 11/17 BJT amplifiers (PDF)

• Lab Report #3 Due at 5:00 pm Monday, 11/23

• Lab 10 11/24 BJT Common Base Amplifier and Logic Inverter (PDF)

• Lab 11 12/1 BJT Design Problem*

• Lab Report #4 Due at 5:00 pm Monday, 12/7

• Lab Notebooks handed in for grading by 5:00 pm Monday 12/7

• Datasheets

opamps: LM741(National) LM741(Fairchild) OP27 OP37 AD8045

diodes: 1N4148 1N4001/2/3/4 1N4733 (5.1V Zener)

transistors: 2N7000 (n channel MOSFET)

2N4124 (npn transistor similar to 2N3904)    2N4126 (npn transistor similar to 2N3906) BD249 (NPN Power Transistor)

CD4007 (CMOS transistor array, TI datasheet; the Fairchild datasheet is here )

• Spice Models

2N4124 (npn transistor similar to 2N3904)    2N4126 (npn transistor similar to 2N3906)

(* asterisk indicates lab activity in which students are building circuits of their own design)

Links

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This page is maintained by David Dickensheets.