EE371 Quizes and Tests Fall 1998
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EE371 Quiz #1
September 14, 1998
1 DESCRIBE THE INSTRUCTION EXECUTION
CYCLE FOR THE PICOPROCESSOR
JMP $1234
INSTRUCTION STARTING WITH "FETCH THE
OPCODE" AND ENDING WITH "INCREMENT THE
PROGRAM COUNTER"
Fetch the opcode for the JMP instruction
Decode the opcode
Increment the program counter to point to the first
byte of the address
Fetch the first byte of the address and save in a
temporary register
Increment the program counter
Fetch the second byte of the address and save in the
temporary register
Transfer the temporary address register to the
program counter
[This is the end of the JMP $1234 instruction.
Incrementing the program counter again really belongs
to the action in the next instruction]
2 WHAT IS THE FUNCTION OF THE PROGRAM
COUNTER?
To generate the address in memory from which the
next op code is fetched.
3 WHAT IS THE BASIC FUNCTION OF THE
SEQUENCE CONTROLLER?
To generate the control signals at the proper time to
effect the instruction.
EE371 Quiz #2
October 2, 1997
1. AN 8-BIT 2'S COMPLEMENT NUMBER IS
1 1 1 0 1 . 1 1 0
WHAT IS ITS DECIMAL EQUIVALENT?
The number is a negative number because the most significant bit is 1.
So, take the two's complement to find the magnitude
0 0 0 1 0 . 0 1 0 = +2.25
so
1 1 1 0 1 . 1 1 0 = -2.25
2. FIND THE SIGNED MAGNITUDE BINARY CODE USING 5 INTEGER AND 3 FRACTIONAL BITS (LIKE THAT ABOVE) FOR THE DECIMAL NUMBER -10.75.
The magnitude is 1010.110 and the sign is negative, so the answer is
11010.110
3. THE HC12 ADDS THE FOLLOWING BINARY NUMBERS:
0 1 0 1 1 0 1 1
0 0 1 0 1 1 0 1
1 0 0 0 1 0 0 0 = $88
GIVE THE RESULT (IN HEXADECIMAL) AND STATE WHAT IS IN EACH OF THE CCR BITS
N = 1
Z = 0
V = 1
C = 0
EE 371 First Semester Test - Monday September 21, 1998
20 Points, 15% of Final Grade
Please put your name on the outside of the paper alsoName ___KEY: T1F98KEY.WPD_______________
1. Imagine the picoprocessor designed in chapter 2 of Microcontrollers and Microcomputers having a 16-bit
register like the D register in the M68HC12. Give the sequential steps, starting with "Fetch the op
code" and ending with "Increment the program counter" which describe the execution cycle for an
instruction that loads this 16-bit register from a memory location specified in the instruction (i.e. using
the extended addressing mode of the M68HC12.) (4 points)
Fetch the op code
Decode the op code
Increment the program counter
Fetch the first half of the effective address into a temporary address register
Increment the program counter
Fetch the second half of the effective address into a temporary address register
Transfer the effective address of the data into the memory address register
Fetch the first byte of the data into « of the D register
Increment the temporary memory address register
Fetch the second byte of data into the second « of the D register
Increment the program counter
2. A HALT instruction is to be added to the picoprocessor. It should stop any further operation until the
reset switch is pressed. Describe how this could be done. (4 points)
After the op code is decoded, the sequence controller could reset a bit which is ANDed with the clock. This
would stop all futher clocks from going to the sequence controller. The bit would be set when the sequence
controller is reset by the RESET signal.
3. For each of the following M68HC12 instructions, explain where the data comes from (the source) and
where it is going (the destination). (8 points)
LDAB #$40 From the memory location immediately following the op code byte
To Accumulator B
STAA 6,x From accumulator A
To the memory location pointed to by the sum of the contents of
the X register plus the offset 6.
LDX $1234 From memory locations $1234 and $1235
To the X register
LDAA $06 From memory location $0006
To accumulator A
4. What D-Bug12 monitor command is used for: (4 points)
Displaying memory? MD
Displaying registers? RD
Start assembling a program at $0800? ASM 800
Start executing a program at $0800? G 800
EE 371 QUIZ #3 October 30, 1998
Name __________________________________________
WRITE STRUCTURED HC12 ASSEMBLY CODE SEGMENTS FOR THE FOLLOWING DESIGNS. YOU MAY USE YOUR CPU12 REFERENCE GUIDE:
ASSUME: K1 AND K2 ARE UNSIGNED 8-BIT BINARY NUMBERS IN MEMORY LOCATIONS WITH LABELS K1 AND K2
1. DO
do_loop:
K1 = K2
movb K2,K1
K2 = K2 + 1
inc K2
ENDDO
WHILE (K2 < !122)
ldaa K2
cmpa #!122
blo do_loop
2. IF K1 = K2
ldaa K1
cmpa K2
bne else_part
THEN K2 = !26
moveb #!26,K2
bra endif
ELSE K1 = K2
elsepart:
movb K2,K1
ENDIF
endif:
EE 371 Second Semester Test - Monday October 12, 1997
40 Points, 15% of Final Grade
Please put your name on the outside of the paper alsoName ______KEY_________________
1. Give the requested codes for the following data. Assume all binary codes are 8 bits with 5 integer
(including a sign bit if necessary) and 3 fractional bits. (12 points)
Decimal
Information Unsigned Two's Complement Signed/Magnitude
12.375 0 1 1 0 0 . 0 11 0 1 1 0 0 . 0 1 1 0 1 1 0 0 . 0 1 1
-13.875 Not possible 1 0 0 1 0 . 0 0 1 1 1 1 0 1 . 1 1 1
2. The data in memory location $6000 - $600F, as shown by a MD 6000 command in the Dbug-12
monitor is:
6000 23 42 94 00 - 60 00 65 02 - 11 22 48 65 - 6C 70 4D 65 #B..`.e.."HelpMe
Give the results (in hex) of the following instructions which are executed in sequence. (10 points)
ldx #$6000 X = $6000
ldaa 4,x A =$60
ldab 5,x B = $00
ldd 4,x D = $6000
ldaa [4,x] A = $23
The following instruction sequence is executed;
ldaa #$56
cmpa $6002
State whether or not the following conditional branch instructions are taken: (8 points)
BNE? YES BLE? NO BHI? NO BLS? YES
3. Write an HC12 program that will do the following. Put your code in the blank lines following the
comments. (10 points)
ORG $4000
; Initialize the stack pointer to $0a00
LDS #$0A00
; Initialize the X register to point to $5000
LDX #$5000
; Transfer bytes from memory locations $5000 - $5014 to $6000 - $6014
LDY #$6000
LDAB #$15
LOOP:
MOVB 1,X+,1,Y+
DBNE B,LOOP
; Return to the Dbug-12 Monitor
SWI
EE 371 Third Semester Test - Monday November 9, 1998
50 Points, 15% of Final Grade
Please put your name on the outside of the paper also Name ___KEY______________
1. Assume K1, K2 and K3 are unsigned 8-bit integers.
a. Show how to allocate storage for these variables assuming the following memory map equates: (6
points)
ROM: EQU $4000
RAM: EQU $6000
org RAM ; Allocate data storage
K1: DS 1
K2: DS 1
K3: DS 1
b. Write HC12 assembly language code to implement the design segment below (24 points)
; Initialize K3 = 1
movb #!1,K3
; . . . Some unknown code is here. You don't have to do anything.
; Now provide HC12 code for the following design segment
; DO
while_start:
; K1 = K2
movb K2,K1
; IF (K2 = K3)
ldaa K2
cmpa K3
bne else_part
; THEN
; K2 = K2 + 1
inc K2
bra endif
; ELSE
; K2 = K2 - 1
else_part:
dec K2
; ENDIF
endif:
; K3 = K3 + 1
inc K3
; ENDDO
; WHILE ( K3 < !10 )
ldaa K3
cmpa #!10
blo while_start
; ENDWHILE
2. Give short answers to the following:
What are polled interrupts? (4 points)
A CPU which implements polled interrupts must interrogate or poll each of the potential
interrupting devices after an interrupt has occurred to determine which of them has generated
the interrupt request. This is done by reading a status register in each of the devices looking for
an "I did it bit."
The HC12 is a vectored interrupt processor. Describe how the HC12 (operating without the D-bug12
monitor) uses a vector to find the correct interrupt service routine after an interrupt occurs. (8 points)
A vector is a pointer to the correct interrupt service routine. Each of the interrupting devices
(timer overflow, output compare etc) has a dedicated memory location for this vector. When an
interrupt occurs, the CPU pushes all registers onto the stack and then retrieves the vector from
the vector location. It then starts executing the interrupt service routine starting at this location.
What initialization has to be done in an HC12 program to have interrupts operating when the timer
overflow flag is set? Assume you are working in the lab with the Dbug-12 monitor on the EVB. (8
points)
Initialize the interrupt service routine vector using the D-bug12 monitor routine SetUserVector
Enable the timer
Reset the TOF flag
Enable the TOF interrupt
Unmask the I bit
EE 371 Final Exam - 1998
35 Points, 25% of Final Grade
Please put your name on the outside of the paper also Name ______Key______________
Note: Active low signals are denoted by an *, e.g. O1*
Give short answers to questions 1 - 4: (4 points each)
1. What is a data bus?
A bidirectional, parallel (multiple lines) information pathway with multiple sources and destinations.
2. How is an information source, such as a set of switches, interfaced to a data bus?
By using tri-state gates whose enable signal is a combinational logic signal derived from an address decoder (to select one of many) and a read control signal to control the timing of the information transfer onto the data bus.
3. How is an information destination, such as an array of LEDs, interfaced to a data bus?
By using latches whose clock signal is a combinational logic signal derived from an address decoder (to select one of many) and a write control signal to control the timing of the information transfer from the data bus.
4. How is the problem of multiple sources of information present on a data bus solved in most microcomputer systems?
Multiple sources can exist as long as addressing and address decoding is used to enable one and only one source through tri-state gates on the data bus at any one time.
Answer questions 5 - 7 assuming the following address decoder using a 74LS138: (2 points each)
5. What address causes the O2* output to be asserted? $22
6. The address $25 is applied. What output is asserted? O5*
7. The address $35 is applied. What output is asserted? None
Define the following terms: (2 points each)
8. RAM - Random Access Memory
9. EEPROM - Electrically Erasable Programmable Read Only Memory
10. EPROM - Erasable Programmable Read Only Memory
11. Dynamic RAM - Random Access Memory whose storage cell is a capacitor.
12. List the programming steps necessary to be able to use an M68HC12 internally generated interrupt, such as the timer overflow or input capture. (5 points)
Initialize the interrupt vector
Enable the interrupting device
Clear any interrupting flag
Unmask global interrupts