EE361 Quizes and Tests Fall 1997
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EE361 Quiz #1
September 15, 1997
1 DESCRIBE THE INSTRUCTION EXECUTION CYCLE FOR THE
PICOPROCESSOR
MVI A,65
INSTRUCTION STARTING WITH "FETCH THE OPCODE" AND ENDING
WITH "INCREMENT THE PROGRAM COUNTER"
Increment the program counter
Fetch the opcode
Decode the opcode
Increment the program counter to point to the data
Fetch data from memory into the A register
Increment the program counter to point to the next opcode
2 AN 8-BIT 2'S COMPLEMENT BINARY NUMBER IS
10110.011
GIVE ITS DECIMAL EQUIVALENT -9.625
3 FIND A 2'S COMPLEMENT BINARY CODE FOR THE DECIMAL NUMBER
10.5
01010.1
EE361 Quiz #2
October 2, 1997
1. THE BUFFALO MONITOR MD D000 COMMAND DISPLAYS THE FOLLOWING:
D000 82 34 76 0F 08 22
GIVE THE RESULT IN THE REGISTER AFTER THE FOLLOWING INSTRUCTIONS ARE EXECUTED:
LDAB $D003 B = 0F
LDAA #$D0 A = D0
LDX #$D000 X = D000
LDX $D001 X = 3476
2. THE DATA IN MEMORY LOCATION $D000 IS ENCODED WITH A 2'S COMPLEMENT BINARY CODE. WHAT IS IT DECIMAL VALUE?
The data is $82 - %10000010 = -128 + 2 = -126
EE 361 First Semester Test - Tuesday September 32, 1997
30 Points, 20% of Final Grade
Please put your name on the outside of the paper alsoName _______________________
1. An 8-bit adder circuit in an ALU produces the sum of two 8-bit numbers and the sign (N), zero (Z), 2's-complement overflow (V) and carry condition code register bits. For each of the following additions,
give the correct binary sum and the results in the N Z V C bits. (12 points)
(a) 0 0 1 0 1 1 0 1 (b) 1 0 0 1 0 0 0 1
1 1 0 1 1 0 1 1 1 0 1 0 1 1 1 1
0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0
N=0 Z=0 V=0 C=1 N=0 Z=0 V=1 C=1
2. Assume each of the binary numbers in question 1 are encoded with an 8-bit unsigned binary code. Give
the decimal value of each of the two operands and each result for 1(a) and 1(b). (6 points)
(a) 45 (b) 145
+219 +175
8 64
3. Assume each of the binary numbers in question 1 are encoded with an 8-bit 2's-complement binary code.
Give the decimal value of each of the two operands and each result for 1(a) and 1(b). (6 points)
(a) +45 (b) -111
+-37 + - 81
+ 8 64
4. Complete the state transition diagram for a picoprocessor instruction that loads the A register with data
in memory using extended memory addressing. The format of the instruction is: the opcode (one byte)
followed by the 16-bit (two bytes) address of the data. (6 points)
The complete diagram will have the following steps:
1. Fetch the Instruction
2. Increment the PC to point to the first byte of the address of the data
3. Fetch the first byte of the address into the temporary
address register
4. Increment the PC to point to the second byte of the
address of the data
5. Fetch the second byte of the address into the
temporary address register
6 Transfer the temporary address register into the
memory address register
7. Fetch the data into the A register
8. Increment the PC to point to the next instruction
EE 361 QUIZ #3 October 30, 1997
Name_________________________
Use the following pseudo-code to produce an HC11 program. Assume: K1 is an UNSIGNED
8-bit Integer and that MAX = 12710. Assume a function to PRINT "ERROR" can be called by
JSR PR_ERROR. Insert your HC11 code in the comments below: If you can't remember an
op code, make one up and define what it is supposed to do.
MAX EQU 127 Note:
* IF K1 > MAX The shift instructions are:
ldaa K1 ASLA - Arith Shift Left A
cmpa #MAX ASRA - Arith Shift Right A
bls else_part_1 LSLA - Logic Shift Left A
* THEN K1 = K1/2 LSRA - Logic Shift Right A
lsra Divide by 2
staa K1 Restore K1
bra endif_1
* ELSE
else_part_1
* K1 = K1 + 1
inc K1
* IF K1 Overflows
bcc no_overflow
* THEN
* PRINT "ERROR"
jsr PR_ERROR
no_overflow
* ENDIF K1 Overflows
endif_1
*ENDIF K1 > MAX
EE 361 QUIZ #4 December 4, 1997
Name ______________________________
1. What must be initialized to enable a timer interrupt in an HC11 system
using the Buffalo Monitor?
Initialize the stack pointer
Initialize the jump vector table
Clear the interrupt causing flag, e. g., TOF
Enable the timer interrupt, e.g. TOI
Unmask the global interrupt bit
(Need at least 3 for full credit)
2. For an HC11 without a Buffalo Monitor, where are the interupt vectors located?
$FFC0 - $FFFF
3. Which HC11 instruction unmasks global interrupts?
CLI
4. In an HC11 interrupt service routine you MUST push all registers onto the stack -
True or False?
FALSE, the HC11 pushes the registers automatically.
EE 361 Second Semester Test - Tuesday October 14, 1997
30 Points, 15% of Final Grade
Please put your name on the outside of the paper alsoName _____Answer Key________
1. The following program has been downloaded and run on the EVB. The register display, BEFORE the
program is executed, shows: P-FFFF Y-1234 X-1000 A-03 B-54 C-D0 S-4A
0002 c000 org $c000
0003 c000 8e df ff lds #$dfff
0004 c003 36 psha
0005 c004 bd c0 08 jsr sub
0006 c007 3f swi
0007 c008 37 sub pshb
0008 c009 36 psha
0009 c00a 01 nop
0010 c00b 33 pulb
0011 c00c 32 pula
0012 c00d 39 rts
Complete the register display that will be shown
AFTER the program has executed.
P- C007 Y-_1234__ X-_1000__ A-_54____
B-__03___ C-D8 S-_DFFE__
The stack used by this program is located in
memory locations $DFFB-$DFFF. Give the
contents of these memory locations AFTER the
program has executed.
$DFFB __03___
$DFFC __54___
$DFFD __C0___
$DFFE ___07__
$DFFF ___03__ (10 points)
2. For each of the following code snippets, state if the branch is taken (Y or N):
ldaa #$80 . ldaa #$FF . ldaa #$FF
bpl SAM cmpa #$FE cmpa #$FE
bhi GEORGE bgt SUE
Y ___or N _X_ Y _X_ or N ___ Y _X_ or N ___ (6 points)
3. When using the lab EVBs to emulate a dedicated application system with fixed ROM and RAM, show
the EQUs appropriate to locate your program, stack and variable data:
CODE EQU __$C000___
DATA EQU __$D000___
STACK EQU __$DFFF___ (6 points)
Where, and how, should constants (such as messages to be printed) be located in your program?
(4 points)
Constants should be in ROM and can be anywhere as long as they are not executed. They do not have to be
located at some specific place. You can use the FCB, FCC and FDB directives to define the memory constants.
4. Give the M68HC11 addressing mode for each of the following instructions:
ldaa $23 _Direct___ ldaa #$23 __Immediate
ldaa $23,X _Indexed__ aba __Inherent (4 points)
EE 361 Third Semester Test - Tuesday November 18, 1997
40 Points, 20% of Final Grade
The notation used for an asserted low signal is /READ (read-bar)
Please put your name on the outside of the paper alsoName _______________________
1. Assume K1 and K2 are labels on memory
locations containing unsigned 16-bit
integers. Write HC11 assembly language
code to implement the design segment
below (10 points)
* IF K1 K1
* DO
* K2 = K2-1
* IF K2 = K3
* THEN K1 = K1 + 1
* ENDIF K3 = K2
* ENDO
* ENDWHILE K2 > K1
Solution:
* WHILE K2 > K1
whilestart
ldaa K2
cmpa K1
ble endwhile
* DO
* K2 = K2-1
dec K2
* IF K2 = K3
cmpa K3
bne endif
* THEN K1 = K1 + 1
inc k1
* ENDIF K3 = K2
ENDIF
* ENDO
bra whilestart
* ENDWHILE K2 > K1
endwhile
3. An 11-bit address is applied to two 74LS138 1-of-8 decoders as shown in the figure. For which address
(in hex) is the /ADR_OK signal asserted? (5 points)
4. Design an input interface for a computer whose CPU has an 8-bit data bus and an 11-bit I/O address bus.
The CPU generates /READ and /WRITE control signals when it is reading and writing respectively.
The input device attached to this interface is to be a set of 8 switches. The 4 most significant (B7-B4)
are to provide a logic 0 when open and logic 1 when closed. The 4 least significant (B3-B0) are to
provide a 1 when open and a 0 when closed. Your design must show how to wire the switches, the
details of the address decoder to fully decode the 11-bit address $1A7, and the appropriate bus interface
circuits. Use a separate piece of paper. (15 points)
E.E. 361 Final Exam, December 15, 1997
50 Points, 25% of the final grade
Open Book - Open Notes
Name______KEY__________________________
Please put your name on the outside of your papers
1. Refer to the picoprocessor design given as Figure 2-14 on page 23 of Microcontrollers and
Microcomputers. Describe the purpose of the blocks labeled: (3 points each)
a. Status
The status bits contain information about the last ALU operation is used by the sequence controller for executing
conditional branch instructions.
b. Sequence Controller
The sequence controller is the brains of the computer. It takes the decoded instruction code and produces correctly
timed control signals in the correct sequence to execute the instruction.
c. Temporary Address Register
This holds an address temporarily while it is being fetched from memory. For example, when a jump instruction is
being executed, the PC is used to fetch the destination or jump address. This is fetched in two bytes and put into
the TAR until it can be transferred to the PC for the next instruction.
2. The M68HC11 fetches the op code to be executed at the start of each instruction execution cycle. More
modern CPUs have an instruction-fetch pipeline (or cache) which is filled by the CPU fetching bytes from
memory while it (the CPU) is doing some other internal operations. For example, at the same time the
CPU is adding the A to the B registers, which is an internal operation, it can be fetching another byte from
memory to put into the instruction pipeline. Explain how this strategy can improve the performance of the
CPU. (3 points)
This speeds up the operation of the cpu by eliminating or reducing the clock cycles spent fetching op code bytes.
The system breaks down when the next instruction to be executed, say after a jump, is not in the instruction fetch
pipeline.
3. Numbers ranging from -5.000 to +5.000 are to be encoded with a binary code to a resolution of 0.125 (i.e.,
there should be a separate code for -5.000, -4.875, -4.75, ...).
a. Define a code (the number of bits and the coding scheme) that can do this. (5 points)
I would use a 7 bit, 2's-complement code with 4 integer bits (including the sign bit) and 3 fractional bits.
b. Demonstrate how your code works by giving the codes for +5.000, +1.25 and -5.000. (3 points)
+5.000 = 0101.000 +1.25 = 0001.010 -5.000 = 1011.000
4. The M68HC11 has 5 addressing modes that can be used with the ldaa instruction. State what they are,
give an example, and describe how each mode works. (10 points)
Immediate ldaa #26 The data for the instruction immediately follows the op code in the program
memory.
Direct ldaa $22 The data for the instruction resides in memory in the first 256 locations (i.e.
addresses $0000 - $00FF
Extended ldaa $1234 The data for the instruction resides in memory space with addresses $00100 -
$FFFF.
Indexed X ldaa $10,x The effective address of the data is at the offset plus the contents of the x register.
In this case, x+$10
Indexed Y ldaa $10,y Same as indexed X addressing except the offset is added to the y register to find the
effective address.
5. An 11FC68 microcontroller has two 8-bit output ports (called P and Q) and two 8-bit input ports (called R
and S). Assume Port R is connected to a set of eight switches from which you want to receive information.
Describe how you would implement a scheme using these resources that would allow you to input data
from the switches only after the user has completed entering new data. Your answer must discuss both
software and hardware issues. (10 points)
Handshaking must be added to the design. In this case, the most simple design would be to use polling I/O. An
additional switch and a latch or flip-flop must be included in the hardware design. The switch is a push button
switch which sets the latch when the user has finished entering the data on the 8-switch bank. The output of the
latch is connected to one of the bits on the other input Port S. The latch is reset by connecting its reset line to one
of the bits on the bits on either output Port P or Q. The user's program then can poll the latch by reading from Port
S. When the latch is set, the switch bank, Port R, can be read. After reading the data, the reset signal for the latch
can be asserted to reset it.
6. Write a program with an interrupt service routine for an M68HC11 on an EVB using the Buffalo Monitor.
The program is to use the Timer Output Compare 2 to generate interrupts at a frequency of 400 Hz. The
main program must show how to initialize the TOC2 interrupts. The foreground task is a simple spin loop
doing nothing. Your interrupt service routine has no task to perform other than to get ready for the next
interrupt. The program must be commented. Use the back of page 1 for your program. (10 points)
Assembler release TER_2.0 version 2.09
(c) Motorola (free ware)
0001 * MC68HC11 Example
0002 * Final exam F 97 problem 6
0003 * Generate a 400 Hz interrupts
0004 * File: FF97INT.asm
0005 * Monitor Equates
0006 * Constant Equates
0007 * 400 Hz is 2.5 ms period
0008 1388 CLOCKS EQU 5000 Num clocks for 2.5 ms
0009 * I/O Register Equates
0010 1000 REGS EQU $1000
0011 000e TCNT EQU $0E TCNT register
0012 0023 TFLG1 EQU $23 TFLG1 offset
0013 0018 TOC2 EQU $18
0014 0040 OC2F EQU %01000000 Output compare 2 Flag
0015 0040 OC2I EQU OC2F Interrupt enable
0016 0022 TMSK1 EQU $22 Timer mask reg
0017 * Memory Map Equates
0018 c000 PROG EQU $C000 ROM location
0019 d000 DATA EQU $D000 RAM location
0020 dfff STACK EQU $DFFF Stack pointer location
0021 00dc OC2VEC EQU $00DC OC2 Interrupt jump
0022 *
0023 00dc ORG OC2VEC
0024 00dc 7e c0 13 jmp isr
0025 c000 ORG PROG
0026 prog_start
0027 c000 8e df ff lds #STACK
0028 c003 ce 10 00 ldx #REGS
0029 * Grab the value of the TCNT register
0030 c006 ec 0e ldd TCNT,X
0031 c008 ed 18 std TOC2,X
0032 * Now have 32 ms to set up the system
0033 * Set up interrupts
0034 c00a 86 40 ldaa #OC2F
0035 c00c a7 23 staa TFLG1,X Clear OC2F
0036 c00e a7 22 staa TMSK1,X Enable OC2 Interrupt
0037 c010 0e cli Unmask global interrupts
0038 * Wait until the counter is 0
0039 c011 26 fe spin bne spin
0040
0041 * Interrupt Service Routine
0042
0043 c013 ce 10 00 isr ldx #REGS
0044 * Set up TOC2 for the next interrupt
0045 c016 ec 18 ldd TOC2,x
0046 * Add clock pulses
0047 c018 c3 13 88 addd #CLOCKS
0048 c01b ed 18 std TOC2,x
0049 * And clear the OC2F
0050 c01d 86 40 ldaa #OC2F
0051 c01f a7 23 staa TFLG1,x
0052 c021 3b rti
0053
Program + Init Data = 37 bytes
Error count = 0