Final Exam Fall 96
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EE361 Quiz #1
September 11, 1996
EXPLAIN THE FOLLOWING TERMS
1 REGISTER ADDRESSING
An addressing mode used for an instruction whose data are in registers.
2 IMMEDIATE ADDRESSING
An addressing mode used for an instruction whose data immediately follow the op
code.
3 SEQUENCE CONTROLLER
Hardware within the CPU which generates correctly timed control signals to control
all operations.
4 A CONTROL INSTRUCTION
An instruction which causes some transfer of control within a program, for
example, a branch instruction.
5 INSTRUCTION EXECUTION CYCLE
The sequence of steps, including instruction fetch, decode, etc, that the cpu goes
through to execute any particular instruction.
EE361 QUIZ #2
September 25, 1996
THE MEMORY DISPLAY SHOWS:
D000 08 29 3F 7F 86 99 A0 64 . . .
AND THE CURRENT VALUE IN THE X REGISTER IS
$D000.
GIVE THE RESULTS OF THE FOLLOWING
INSTRUCTIONS
LDAA $D003 A = 7F NZVC = 000-
LDAB 4,X B = 86
LDY $D001 Y = 293F (Y is a 16-bit register)
NOW, WITH THESE VALUES IN THE A AND B
REGISTERS THE FOLLOWING INSTRUCTIONS ARE
EXECUTED:
CBA
BLT SOMEPLACE
IS THE BRANCH TAKEN? NO. A is less than B in 2's
complement
(You may use the Nerd Book)
EE361 QUIZ #3, 4 November 1996
Consider the design of an input interface for a CPU with
external address, data and control buses:
1. What control signal is produced by the CPU when doing
an input operation?
READ or RD
2. Why is this control signal required?
This signal is both an indication of direction of data
flow and a timing signal. It is needed to enable the
tristate gates at the correct time to put input data onto
the data bus for the CPU to take it.
3. Describe how you would build an address decoder to
fully decode an 8-bit I/O address.
An 8-bit decoder is needed. One way to do that would
be to use two 74LS138 3-8 decoders in cascade. I would
put address bits A3, A4 and A5 on one decoder address
inputs and A0, A1, and A2 on the other. A6 and A7
would be used as enable bits on each decoder and the
other enable bits would be tied high or low depending
on what A6 and A7 are.
4. What hardware is necessary to connect the source of the
data onto the data bus?
Tristate or three-state buffers.
EE361 QUIZ #4 December 4, 1996
1. What are the mnemonics RTS, CTS, DSR and TXD
abbreviations for?
RTS = Request to Send
CTS = Clear to Send
DSR = Data Set Ready
TXD = Transmit Data
2. Draw a UART showing parallel and serial buffers,
registers and clock signals. Clearly indicate transmit
and receive signals and data.
See Figure 10.2.
EE361 Test #2 November 26, 1996
45 Points, 20% Final Grade
Name___SOLUTION__________________
Please put your name on the outside of the paper also
1. Assume K1, K2, and K3 are unsigned, 8-bit integers in memory locations K1, K2 and K3.
Write a section of M68HC11 code to implement each of the following pseudocode designs.
The code is to follow the EE361 Assembly Coding Specifications. [Use a separate piece of
paper (or the back of this) to write your HC11 code.] (20 points)
a. * IF K1 not equal to K2
ldaa K1
cmpa K2
beq elsepart
* THEN
* K1 = K2
ldaa K2
staa K1
bra endif
* ELSE
* K1 = 2 * K2
elsepart
ldaa K2
asla Multiply by 2
staa K1
endif
* ENDIF K1 not equal to K2
b. * WHILE K3 < K2
whilestart
ldaa K3
cmpa K2
bhs endwhile
* DO
* K3 = K1 + 1
ldaa K1
inca
staa K3
* K2 = K2 - 1
dec K2
bra whilestart
ENDO
endwhile
* ENDWHILE K3 < K2
2. An I/O interface requires address decoding and timing signals that are generated by the
CPU.
a. What purpose does address decoding provide? (5 points)
To select the proper I/O device.
b. What timing signal is necessary for an output operation and what function does it provide?
(5 points)
WRITE, E, RW: To indicate when the CPU has placed output data on the data bus.
3. A 74LS138 decoder has the following inputs, where ADR5-ADR0 are bits from a 6-bit
address bus:
A2=ADR5, A1=ADR4, A0=ADR3, 1=ADR2, 2=ADR1 E3=ADR0.
What address is the 6 output decoding? (5 points)
The address is %110001 = $31
4. Interrupt latency is the time interval between an interrupt request and the start of the interrupt
service routine.
a. Give two components of interrupt latency. (5 points)
Completion of the current instruction; time spent finding the correct ISR; time spent pushing
data onto the stack
b. Describe how you could measure interrupt latency in the lab using the EVB and other lab
instrumentation. (5 points)
Use a signal generator to generate a repetitive IRQ. In the ISR, set and then reset a bit on an
I/O port each time you enter the ISR. Use a scope to measure the time between the IRQ and
the bit set in the ISR. To be more accurate, you should subtract the number of cycles taken
in the ISR to toggle the output port bit.
Another possibility is to use the TOC to generate an interrupt. The value of the TOC register
then has a record of the exact time the interupt occurred. The first thing to do in the ISR is
to read the TCNT register again. The difference in the two readings give the number of e-clock cycles elapsed since the interrupt occurred.
E.E. 361 Final Exam, December 11, 1996 ANSWER KEY
50 Points, 25% of the final grade
Open Book - Open Notes
Name___________________________________
Please put your name on the outside of your papers
1. An EE class needs a binary code to encode each of 42 students.
a. Specify the type of code and the fewest number of bits to best encode this information. (5 points)
Unsigned Binary, 6 bits
b. The professor uses a binary number system to encode test scores, which may range from -100 (base 10) to
+100 (base 10) in steps of 1 point. Specify the type of code and the fewest number of bits to best encode
this information. (5 points)
Two's-complement, 8 bits
c. The professor uses hexadecimal numbers to encode the final grades, which range from 0 to 100 (base 10) in
steps of 1 point. How many hexadecimal digits are required and what is the maximum grade, in
hexadecimal, that a student can earn? (5 points)
2 hex digits, maximum score is $64
2. A 10-bit successive approximation A/D converter has the following specs:
Minimum conversion time: 0.1 msec; input voltage: -5 to +5 volts
a. What is the maximum frequency that can be sampled without aliasing? (5 points)
fmax = 1/2*conversion time = 5000 Hz
b. For this frequency, what is the aperture time required so that errors in sampling are less than plus
or minus 1/2 least significant bit? (5 points)
tap = 1 / 2 *pi*fmax*2n = 1 / 2*pi*5x103*210 = 3.11x10-8 = 31.1 ns
c. What is the resolution of this A/D in volts? (5 points)
Resolution = 10v/1024 = 0.0098v ~ 10 mv
3. From your understanding of the operation of computers, discuss the instruction execution cycle as it
applies to the M68HC11 executing a memory write operation such as a STAA DATA instruction where
DATA is located in memory location $D000. Hint: Assume the instruction execution cycle starts with the
program counter pointing to the first byte of the STAA DATA instruction and is finished when the
program counter points to the next instruction. Your discussion should include, but not be limited to:
control signals generated by the CPU; memory operations; e-clock cycles used. DO NOT discuss detailed
memory timing issues. Use an extra sheet of paper to answer this question and write so I can read it. (20
points)
1. CPU puts the address of the STAA DATA instruction (from the PC) onto the address bus and
fetches the STAA op code (1 E-clock)
2. CPU decodes the op code and sees that it is an extended address instruction and that a two byte
address has to be fetched.
3. The PC is incremented, the address is put on the address bus, and the first byte of the DATA
address is fetched (1 E-clock)
4. The PC is incremented, the address is put on the address bus, and the second byte of the DATA
address is fetched (1 E-clock)
5. The two byte address that was fetched is put on the address bus and the CPU lowers the R/W* write
control signal.
6. The data in the ACCA is put on the data bus.
7. The CPU raises the R/W* signal to latch the data into the memory. (1 E-clock)
8. The PC is incremented to point to the next instruction.