Fredrick M. Cady
Department of Electrical and Computer Engineering
Montana State University
Bozeman, MT 59715
fcady(aatt_sign)ece.montana.edu
I teach my courses, because I think we learn best, by first teaching something about the hardware and then some software and then by practicing in the laboratory. We then repeat the process by learning more hardware and more software details. At each step of the way, general principles are illustrated by using specific examples from a specific processor. For example, one of the first things we might learn about a processor is what the registers are used for and how the bits in the condition code register are used. After learning the principles and the specifics of these hardware elements, and the part of the instruction set dealing with them, we can go to the laboratory and practice what we have learned.
The organization of Microcontrollers and Microcomputers: Principles of Software and Hardware Engineering (and Software and Hardware Engineering: Motorola M68HC11) generally follows my own course organization. I like to start by explaining the mystery of a stored program computer by creating a plausible design. We then explore the resources of the processor used in the laboratory. Our initial goal is to be able to begin laboratory exercises while teaching other concepts. To do this, we introduce the basic hardware registers, the ALU, and the condition codes. The explanation of the condition code register allows us to discuss binary codes and coding. Special attention is paid to codes used for arithmetic and how the various codes affect the operation of the condition code register.
By this time the student is starting the concurrent laboratory and needs to know how to program the computer. We point out that learning the instruction set of a processor involves knowing what registers are available, what addressing modes have been implemented, and what general categories of instructions are available.
The mechanics of using an assembler are presented so that the student can assemble and run small programs in the laboratory. The complete instruction set for the processor used is covered, at least in instruction categories. It is sufficient at this stage to lead the student through examples using various instructions, particularly those with different addressing modes. Later, as the student matures and gains confidence, more difficult programming assignments can be given.
By now the student is able to write, assemble, download, and run simple programs in the
laboratory. His or her experience will show the need for debugging tools, and we discuss
debugging tools in general in
A large portion of the cost of developing any microcomputer system is the software. A
key chapter in Microcontrollers and Microcomputers: Principles of Software and Hardware
Engineering is dedicated to software design. The basic elements of software design are presented
and the differences between design methodologies and design tools are discussed. Top down
design is presented and pseudo-code, probably the most widely used design tool, is promoted.
This should reinforce software design concepts the student has learned in a previous course. The
student is shown how to use structured programming principles in assembly language. The
design of software modules, with attention paid to reducing interaction between modules, is also
presented.
While the student is tackling more complex programming assignments, bus architectures,
interfaces between external devices and a CPU, and programmed input and output can be
covered. It is here we learn the need for interrupts and real time operations.
By now the student understands that memory stores programs and data. We can discuss
the different types of memory, ROM and RAM, and why a system has both. This is a good time
to discuss the details of memory interfaces and especially timing signals.
Many engineers have a terrible time with serial interfaces, especially the RS-232-C
"standard", because they don't understand why all the signals in the standard interface are there.
Chapter 10 presents a complete description of the handshaking signals developed for
communication channels. Interface cables for various RS-232-C devices are shown, and other
common interface standards such as RS-422, RS-423, and RS-485 are defined.
The text concludes with a discussion of the concepts of A/D conversion and its
companion, D/A conversion.
I would like to thank my wife Katie for her encouragement and assistance with early
versions of the text and Heather Burnham, graduate student in Electrical Engineering for proof
reading help. Thanks also go to several generations of EE361 students at Montana State
University who helped make the text better.
Please let me know if you find other errors. Please use the error submittal form
or email me fcady(aatt_sign)ece.montana.edu. Thanks.
CHAPTER 1. INTRODUCTION
1.1 COMPUTERS, MICROPROCESSORS, MICROCOMPUTERS, MICROCONTROLLERS 1
1.2 SOME BASIC DEFINITIONS 2
1.3 NOTATION 3
1.4 STUDY PLAN 3
CHAPTER 2. THE PICOPROCESSOR: AN INTRODUCTION TO COMPUTER
ARCHITECTURE
2.1 INTRODUCTION 5
2.2 COMPUTER OPERATION CODES 5
2.3 BASIC COMPUTER HARDWARE 6
HARDWARE FOR ADDITION AND SUBTRACTION 6
INPUT AND OUTPUT HARDWARE 8
THE MOVE OPERATION 11
ADDING TWO NUMBERS 12
THE COMPUTER MEMORY 14
THE CONTENTS OF THE COMPUTER MEMORY 14
INSTRUCTION REGISTER AND DECODER 16
PROGRAM COUNTER AND MEMORY ADDRESS REGISTER 18
2.4 COMPUTER TIMING 19
THE INSTRUCTION EXECUTION CYCLE 19
SYSTEM TIMING AND THE SEQUENTIAL STATE MACHINE 19
PROGRAM EXECUTION TIME 23
I/O SYNCHRONIZATION 23
WAIT STATES 24
2.5 MORE INSTRUCTIONS 25
A MORE VERSATILE MOVE INSTRUCTION 25
A MEMORY REFERENCE INSTRUCTION 26
ADDING A CONSTANT TO THE SUM OF TWO VARIABLES 27
2.6 CONTROL INSTRUCTIONS 29
THE HALT INSTRUCTION 29
THE BRANCH INSTRUCTION 29
CONDITIONAL BRANCH INSTRUCTIONS 30
2.7 THE FINAL DESIGN 30
2.8 CHAPTER SUMMARY POINTS 32
2.9 PROBLEMS 32
CHAPTER 3. INTRODUCTION TO THE CPU: REGISTERS AND CONDITION
CODES
3.1 INTRODUCTION 33
3.2 CPU REGISTERS 33
3.3 REGISTER TRANSFERS 34
3.4 YOUR REAL PROCESSOR'S REGISTERS 35
3.5 THE CONDITION CODE REGISTER 35
THE CARRY BIT 35
TWO'S-COMPLEMENT OVERFLOW BIT 37
SIGN BIT 39
ZERO BIT 40
PARITY BIT 40
OTHER CONDITION CODE REGISTER BITS 40
HOW DO THE BITS GET SET OR RESET? 40
USING THE CONDITION CODE REGISTER 41
3.6 THE PROGRAMMER'S MODEL 42
3.7 CHAPTER SUMMARY POINTS 42
3.8 PROBLEMS 43
CHAPTER 4. ADDRESSING MODES
4.1 INTRODUCTION 44
4.2 ADDRESSING TERMINOLOGY 44
4.3 MEMORY ARCHITECTURES 45
LINEAR ADDRESSING 45
SEGMENTED ADDRESSING 46
4.4 ADDRESSING MODES 48
REGISTER ADDRESSING 48
IMMEDIATE ADDRESSING 48
DIRECT MEMORY ADDRESSING 49
INDIRECT ADDRESSING 50
INDEXED AND BASED ADDRESSING 52
RELATIVE ADDRESSING 55
BIT ADDRESSING 56
OTHER ADDRESSING COMBINATIONS 56
4.5 STACK ADDRESSING 57
PUSH AND PULL OPERATIONS 59
SUBROUTINE CALL AND RETURN OPERATIONS 59
4.6 CHAPTER SUMMARY POINTS 61
4.7 YOUR OWN PROCESSOR'S ADDRESSING MODES 61
4.8 PROBLEMS 61
CHAPTER 5. ASSEMBLY LANGUAGE PROGRAMMING AND DEBUGGING
5.1 INTRODUCTION 63
5.2 THE ASSEMBLER 64
ASSEMBLY SOURCE CODE FIELDS 64
MACRO ASSEMBLERS 67
TWO-PASS ASSEMBLERS 69
CROSS ASSEMBLERS AND NATIVE ASSEMBLERS 69
ASSEMBLER OUTPUT FILES 70
5.3 THE CODE LOCATION PROBLEM 70
ABSOLUTE ASSEMBLERS 71
RELOCATABLE ASSEMBLERS 73
5.4 THE LINKER 74
5.5 THE LIBRARIAN 75
5.6 THE LOADER 76
5.7 ASSEMBLY-TIME, LINK-TIME, LOAD-TIME AND RUN-TIME 76
5.8 YOUR ASSEMBLER 77
5.9 THE DEBUGGER 77
PROGRAM DEBUGGING 77
DEBUGGING TOOLS 79
THE DEBUGGING PLAN 81
5.10 TYPICAL ASSEMBLY LANGUAGE PROGRAM BUGS 82
5.11 TRICKS OF THE TRADE 84
5.12 CHAPTER SUMMARY POINTS 85
5.13 PROBLEMS 86
CHAPTER 6. TOP DOWN SOFTWARE DESIGN
6.1 THE NEED FOR SOFTWARE DESIGN 87
6.2 THE SOFTWARE TREE 88
6.3 THE SOFTWARE DEVELOPMENT PROCESS 89
6.4 TOP DOWN DESIGN 90
UNDERSTAND THE PROBLEM COMPLETELY 90
DESIGN IN LEVELS 91
ENSURE CORRECTNESS AT EACH LEVEL 93
POSTPONE DETAILS 93
SUCCESSIVELY REFINE YOUR DESIGN 93
DESIGN WITHOUT USING A PROGRAMMING LANGUAGE 94
6.5 DESIGN PARTITIONING 94
6.6 BOTTOM UP DESIGN 95
6.7 THE REAL WORLD APPROACH 96
6.8 TYPES OF DESIGN ACTIVITY 96
6.9 DESIGN TOOLS 97
STRUCTURED PROGRAMMING 97
PSEUDOCODE 98
USING PSEUDOCODE STRUCTURED ELEMENTS AS A DESIGN TOOL 103
6.10 TOP DOWN DEBUGGING AND TESTING 105
6.11 STRUCTURED PROGRAMMING IN ASSEMBLY LANGUAGE 105
6.12 MODULAR DESIGN 106
MODULE FUNCTION 107
MODULE COUPLING 109
MODULE LOGIC 110
6.13 INTERPROCESS COMMUNICATION 110
INFORMATION IN REGISTERS 111
INFORMATION IN GLOBAL DATA AREAS 111
INFORMATION IN LOCAL DATA AREAS 112
INFORMATION ON THE STACK 112
USING ADDRESSES INSTEAD OF VALUES 113
PASSING BOOLEAN INFORMATION 114
6.14 SOFTWARE DOCUMENTATION 114
SOFTWARE REQUIREMENTS SPECIFICATIONS - SRS 115
SOFTWARE DESIGN DOCUMENT - SDD 115
SOFTWARE CODE 115
SOFTWARE VERIFICATION PLAN - SVP 115
USER MANUALS 115
6.15 CHAPTER SUMMARY POINTS 116
6.16 PROBLEMS 117
CHAPTER 7. COMPUTER BUSES AND PARALLEL INPUT/OUTPUT
7.1 INTRODUCTION 119
7.2 THE COMPUTER BUS 120
INFORMATION SOURCES - THE INPUT INTERFACE 122
INFORMATION DESTINATIONS - THE OUTPUT INTERFACE 123
MULTIPLE SOURCES AND DESTINATIONS 123
TIMING SIGNALS 125
7.3 I/O ADDRESSING 128
MEMORY-MAPPED I/O 129
ISOLATED OR SEPARATE I/O 130
ADDRESS DECODING 133
7.4 I/O SYNCHRONIZATION 139
SOFTWARE I/O SYNCHRONIZATION 140
HANDSHAKING I/O 141
SOFTWARE VERSUS HANDSHAKING I/O 142
I/O SYNCHRONIZATION WITH INTERRUPTS 142
7.5 MORE BUS IDEAS 142
MULTIPLEXED BUS 142
BIDIRECTIONAL BUS TRANSCEIVER 145
SYNCHRONOUS, SEMI-SYNCHRONOUS, AND ASYNCHRONOUS BUSES 146
BUS MASTERS AND SLAVES 147
BUS ARBITRATION 148
ADDITIONAL BUS CONTROL SIGNALS 150
7.6 SIMPLE I/O DEVICES 150
INPUT SWITCHES 150
ARRAYS OF SWITCHES 153
SIMPLE DISPLAY DEVICES 158
7.7 PROGRAMMABLE I/O DEVICES 160
7.8 MORE I/O IDEAS 165
BUFFERED I/O 165
7.9 CHAPTER SUMMARY POINTS 167
7.10 REFERENCES AND OTHER READING 167
7.11 PROBLEMS 168
CHAPTER 8. INTERRUPTS AND REAL-TIME EVENTS
8.1 INTRODUCTION 170
8.2 INTERRUPT SYSTEM SPECIFICATIONS 173
8.3 ASYNCHRONOUS EVENTS AND INTERNAL PROCESSOR TIMING 173
8.4 INTERNAL CPU INTERRUPT HARDWARE 174
8.5 MULTIPLE SOURCES OF INTERRUPTS 176
POLLED INTERRUPTS 177
VECTORED INTERRUPTS 178
MULTIPLE INTERRUPT MASKING 180
8.6 SEQUENTIAL AND NESTED INTERRUPTS 180
8.7 SIMULTANEOUS INTERRUPTS - PRIORITIES 181
SOFTWARE PRIORITY RESOLUTION 181
HARDWARE PRIORITY RESOLUTION 181
8.8 TRANSFERRING CONTROL TO THE INTERRUPT SERVICE ROUTINE 182
8.9 THE INTERRUPT SERVICE ROUTINE - ISR 184
INTERRUPT SERVICE ROUTINE POINTERS 184
INTERPROCESS COMMUNICATION 185
8.10 INTERRUPT ROUTINE RETURNS 187
8.11 OTHER INTERRUPT REQUEST SIGNALS 187
NONMASKABLE INTERRUPTS 187
SOFTWARE INTERRUPT 188
EXCEPTIONS 188
RESET 188
8.12 CONCLUSION AND CHAPTER SUMMARY POINTS 188
8.13 BIBLIOGRAPHY AND FURTHER READING 189
8.14 PROBLEMS 189
CHAPTER 9. COMPUTER MEMORIES
9.1 INTRODUCTION 191
9.2 COMPUTER TYPES AND MEMORY MAPS 191
THE GENERAL PURPOSE COMPUTER SYSTEM 192
THE DEDICATED-APPLICATION SYSTEM 193
9.3 SEMICONDUCTOR RAM 195
MEMORY CELL TYPES 196
STATIC RAM CHIPS 198
DYNAMIC MEMORY 199
DRAM REFRESH 200
PSEUDO-STATIC RAM 201
9.4 ROM MEMORY 201
THE ROM MEMORY CELL 202
PROGRAMMABLE READ ONLY MEMORY - PROM 202
NONVOLATILE RAM - EEPROM AND NVRAM 204
9.5 MEMORY TIMING REQUIREMENTS 206
CPU READ AND WRITE CYCLES 206
MEMORY READ AND WRITE CYCLES 209
9.6 PUTTING IT ALL TOGETHER 214
9.7 CONCLUSION AND CHAPTER SUMMARY POINTS 223
9.8 BIBLIOGRAPHY AND FURTHER READING 224
9.9 PROBLEMS 224
CHAPTER 10. SERIAL INPUT/OUTPUT
10.1 INTRODUCTION 226
10.2 THE COMPONENTS OF AN ASYNCHRONOUS SERIAL COMMUNICATION SYSTEM 226
DATA CODING AND TRANSMISSION 228
DATA TRANSMISSION RATE 229
10.3 STANDARDS FOR THE SERIAL I/O INTERFACE 229
HANDSHAKING SIGNALS 230
COMMUNICATION SYSTEM TYPES 230
HALF-DUPLEX HANDSHAKING SIGNALS 231
DATA TERMINAL EQUIPMENT AND DATA COMMUNICATION EQUIPMENT 232
MODEMS 232
MODEM HANDSHAKING SIGNALS 233
10.4 RS-232-C INTERCONNECTIONS 235
10.5 STANDARD ELECTRICAL SIGNAL LEVELS 237
RS-232-C STANDARD 237
RS-423 STANDARD 238
RS-422 STANDARD 238
RS-485 STANDARD 239
SERIAL INTERFACE ELECTRICAL SPECIFICATIONS 240
10.6 THE UART 241
UART CONTROL REGISTER 244
UART STATUS REGISTER 244
UART ERROR CONDITIONS 244
10.7 ASCII DATA AND CONTROL CODES 244
10.8 FLOW CONTROL 246
10.9 DEBUGGING AND TROUBLE SHOOTING 247
CHOOSE THE CORRECT CABLE 247
CHOOSE THE CORRECT COMMUNICATION PARAMETERS 247
10.10 CHAPTER SUMMARY POINTS 247
10.11 PROBLEMS 248
CHAPTER 11. ANALOG INPUT AND OUTPUT
11.1 INTRODUCTION 250
11.2 DATA ACQUISITION AND CONVERSION 251
11.3 SHANNON'S SAMPLING THEOREM AND ALIASING 252
11.4 ANALOG-TO-DIGITAL CONVERSION 254
A/D CONVERTER TYPES 255
A/D CONVERTER SPECIFICATIONS 259
A/D ERRORS 261
SAMPLE-AND-HOLD 262
CHOOSING AN A/D CONVERTER 263
11.5 DIGITAL-TO-ANALOG CONVERSION 267
D/A CONVERTER TYPES 268
D/A CONVERTER SPECIFICATIONS 269
11.6 OTHER ANALOG I/O METHODS 271
11.7 CHAPTER SUMMARY POINTS 272
11.8 BIBLIOGRAPHY AND FURTHER READING 273
11.9 PROBLEMS 273
APPENDIX A. BINARY CODES
A.1 BINARY CODES REVIEW 275
BINARY CODES FOR NUMERICAL INFORMATION 275
BINARY CODES FOR NON-NUMERICAL INFORMATION 286
A.2 PROBLEMS 288
ANSWERS TO CHAPTER PROBLEMS 425
Return to the top
Errors in
Microcontrollers and Microcomputers: Principles of Software and Hardware Engineering
Page Error Correction Thanks
28 There is an extra bit shown as the carry out of the least significant byte addition. Tim Szaforyn
96 Top line on page: figure 7-4(b) should read Figure 7-3(b) Pam Yakymyshyn
102 The first sentence in the last paragraph would be more clear
if it read:
"Figure 7-9(a) and (b) show an address decoder with multiple ADR_OK outputs, one for each
input and output device. This scheme could be used in a system where the logic circuits
are together on one printed circuit board. On the other hand, in a system like a personal
computer where I/O interfaces may be on separate printed circuit boards that plug
into a motherboard, separate address decoders must be used for each device."
114 In Figure 7-17(a), the timing signal for the latch output should be labeled ADR15-ADR8.
John Glover
125 In the second paragraph, the reference to the
74LS139 in Figure 7-28 should refer to a 74F539 decoder/demultiplexer.
133 In problem 7.12, 297(16) should be 257(16) John Glover
202 The sentance half-way down the paragraph should read:
Working only from the digital values, the digital signal processor must assume
that the sampling criterion has been met and so f(t) is reconstructed not g(t).
David Owenby
220 Example A-3: Resolution should be 2 to the power -3 = 0.125 Jack Borgeson
221 Just below equation (5), the sentence should read. . . For Example A-4, the range is -15.75 to +15.75. Jack Borgeson
222 Equation (9): The answer should be -4.625 Jack Borgeson
231 Answer to problem 3.3(d) should be 34.
244 Problem A.3. The equation -1+(2^(n-1)-1)=2^(n-1) should be -1+(2^(n-1)-1)=2^(n-1)-2. Pam Yakymyshyn
229 In problem A.11, the chapter reference should be
to Chapter 2, not Chapter A.
Request Instructor's Resources
If you have adopted Microcontrollers and Microcomputers: Principles of Software and Hardware Engineering,
Software and Hardware Engineering: Motorola M68HC11, or
Software and Hardware Engineering: Motorola M68HC12 for use in a class and would like to see the instructor's resources
please either email me
fcady(aatt_sign)ece.montana.edu with your class information or fill in the form below.