TABLE OF CONTENTS
CHAPTER 1. INTRODUCTION
1.1 Introduction 1
1.2 Computers, Microprocessors, Microcomputers, Microcontrollers 1
1.3 Some Basic Definitions 3
1.4 Notation 4
1.5 Bibliography and Further Reading 4
1.6 References 4
CHAPTER 2. INTRODUCTION TO THE M68HC12 HARDWARE
2.1 Chapter Pre-study Material 5
2.2 Introduction 5
Two Versions of the M68HC12 8
2.3 The CPU, Registers 9
The Programmer's CPU Model 9
Data Types 11
Control Registers 11
Operating Modes 12
2.4 Background Debug Mode (BDM) 12
2.5 Memory Map 12
2.6 Addressing Modes 13
Immediate Addressing 14
Direct and Extended Addressing 15
Indexed Addressing 15
Inherent Addressing 21
Relative Addressing 22
2.7 Reset 22
The Reset Action 23
Causes of Reset 24
Reset Summary 24
2.8 Conclusion and Chapter Summary Points 25
2.9 Bibliography and Further Reading 25
2.10 Problems 26
CHAPTER 3. AN ASSEMBLER PROGRAM
3.1 Assembly Language Example 27
3.2 M68HC12 CASM12 Assembler 29
3.3 Assembler Source Code Fields 29
Label Field 29
Opcode or Operation Field 30
Operand Field 30
Comment Field 33
3.4 Assembler Pseudo-operations and Directives 35
Assembler Pseudo-operations 36
Assembler Directives 39
Macros 43
3.5 Assembler Output Files 46
3.6 Assembler Invocation 48
3.7 Assembler Errors 48
3.8 Chapter Summary Points 49
3.9 Problems 50
CHAPTER 4. THE M68HC12 INSTRUCTION SET
4.1 Introduction 51
4.2 M68HC12 Instruction Set Categories 51
4.3 M68HC12 Instruction and Operand Syntax 54
4.4 Load and Store Register Instructions 55
Eight-bit Load and Store Instructions 55
Sixteen-bit Load and Store Instructions 58
Stack Instructions 58
Load Effective Address Instructions 66
4.5 Transfer Register Instructions 69
4.6 Move Register Instructions 70
4.7 Decrement and Increment Instructions 70
4.8 Clear and Set Instructions 71
4.9 Shift and Rotate Instructions 72
4.10 Arithmetic Instructions 75
Add and Subtract 75
Decimal Arithmetic 82
Negating and Sign Extension Instructions 83
Multiplication 87
Fractional Number Arithmetic 87
Division 89
4.11 Logic Instructions 91
4.12 Data Test Instructions 91
4.13 Conditional Branch Instructions 93
Signed and Unsigned Conditional Branches 94
4.14 Loop Primitive Instructions 95
4.15 Unconditional Jump and Branch Instructions 97
Branches to Subroutines 97
4.16 Condition Code Register Instructions 100
4.17 Interrupt Instructions 101
4.18 Fuzzy Logic Instructions 101
4.19 Miscellaneous Instructions 101
4.20 Chapter Summary Points 104
4.21 Bibliography and Further Reading 105
4.22 Problems 105
CHAPTER 5. D-BUG12 MONITOR AND DEBUGGER
5.1 M68HC12 EVB D-Bug12 Monitor 109
D-Bug12 Monitor Versions 109
Entering the Monitor 110
Command Line Format 110
5.2 Monitor Commands 110
5.3 Monitor Utility Routines 118
Calling Monitor Routines 119
Summary of D-Bug12 Routines 120
5.4 D-Bug12 Monitor Interrupt Vector Initialization 131
5.5 Operating Hints for the D-Bug12 Monitor 133
5.6 Problems 134
CHAPTER 6. PROGRAMS FOR THE M68HC12
6.1 Assembly Language Programming Style 135
Source Code Style 135
To Indent or not to Indent 143
Upper and Lower Case 143
Use Equates, not Magic Numbers 143
Using Include Files 144
Using Monitor Routines 145
Commenting Style 145
Subroutine or Function Headers 145
6.2 Structured Assembly Language Programming 145
Sequence 146
IF-THEN-ELSE Decision 146
WHILE-DO Repetition 150
DO-WHILE Repetition 152
6.3 Example Programs 152
6.4 Conclusion and Chapter Summary Points 160
6.5 Bibliography and Further Reading 160
6.6 Problems 160
CHAPTER 7. M68HC12 PARALLEL I/O
7.1 Introduction 163
7.2 MC68HC812A4 and MC68HC912B32 163
7.3 Operating Modes 163
Normal Single-chip Mode 164
Normal Expanded Mode 166
Mode Register 168
7.4 The Programmer's I/O Model 169
7.5 M68HC12 Parallel I/O Ports 169
Ports A and B 169
Port C 169
Port D 171
Port E 171
Port F 174
Port G 175
Port H and Port J 176
Port S 177
Port T 178
Port AD 179
7.6 Data Direction Registers 179
7.7 Input and Output Pin Electronics 181
Pull-up Control 181
Reduced Drive 182
7.8 I/O Software 182
Real-time Synchronization 183
Polled I/O 183
7.9 Hardware Handshaking I/O 183
7.10 Chapter Summary Points 187
7.11 Bibliography and Further Reading 187
7.12 Problems 187
CHAPTER 8. M68HC12 INTERRUPTS
8.1 Introduction 188
8.2 M68HC12 and M68HC11 Interrupt Comparison 189
8.3 The Interrupt Process 189
The Interrupt Enable 189
The Interrupt Disable 189
The Interrupt Request 190
The Interrupt Sequence 190
The Interrupt Return 191
8.4 Interrupt Vectors 191
M68HC12 System Vectors 191
Initializing the Interrupt Vectors 193
D-Bug12 Monitor Interrupt Vector Jump Table 193
8.5 Interrupt Priorities 194
8.6 Nonmaskable Interrupts 196
T 197
Clock Monitor Failure 198
Computer Operating Properly - COP 199
Unimplemented Instruction Opcode Trap 201
Software Interrupt - SWI 201
Nonmaskable Interrupt RequestQ 202
8.7 External Interrupt Sources 202
Q 202
Key Wakeups 203
Interrupt Enable and Flags Registers 203
Port J Rising and Falling Edge Selection 205
Port J Pull-up/Pull-down Selection 206
Key Wakeup Initialization 206
8.8 Interrupt Flags 207
Multiple Key Wakeup Interrupts 207
Resetting Interrupt Flags 210
8.9 Internal Interrupt Sources 212
8.10 Advanced Interrupts 212
SharedQ and Parallel I/O Interrupt Vector 212
Polling for Multiple External Devices 213
Selecting Edge or Level Triggering 213
What to do While Waiting for an Interrupt 213
8.11 The Interrupt Service Routine 215
Interrupt Service Routine Hints 215
M68HC12 Dedicated Application System ISR Examples 215
D-Bug12 Monitor ISR Examples 218
8.12 Conclusion and Chapter Summary Points 223
8.13 Bibliography and Further Reading 223
8.14 Problems 223
CHAPTER 9. M68HC12 MEMORIES
9.1 Introduction 226
9.2 M68HC12 Memory Map 226
MC68HC812A4 226
MC68HC912B32 226
9.3 M68HC12 RAM 228
9.4 M68HC12 EEPROM 231
EEPROM Reading 232
EEPROM Control 233
EEPROM Erasing 235
EEPROM Programming 242
Programming EEPROM from EEPROM 244
EEPROM Warnings and Cautions 247
EEPROM Test Register 248
EEPROM Programming Characteristics 249
9.5 MC68HC912B32 Flash EEPROM 251
Flash EEPROM Hardware Interlocks 253
Flash EEPROM Programming Voltage 256
Flash EEPROM Programming 256
Flash EEPROM Erasing 257
Flash EEPROM Programming Characteristics 261
9.6 MC68HC812A4 Expansion Memory 262
Expansion Address Mapping 264
Memory Expansion Control Registers 265
Data Memory Expansion Window 272
Program Memory Expansion Window 272
Extra Memory Expansion Window 276
Register Following Memory Space 277
Programming for Expansion Memory 277
Hints for Using Expansion Memory 285
9.7 Expanded-narrow and Expanded-wide Memory Designs 285
9.8 Clock Stretch Bits 286
9.9 Conclusion and Chapter Summary Points 290
9.10 Bibliography and Further Reading 290
9.11 Problems 290
CHAPTER 10. M68HC12 TIMER
10.1 Introduction 291
10.2 Basic Timer 292
Prescaler 292
Sixteen-bit Free-running TCNT Register 294
Timer Overflow Flag 297
Timer Overflow Interrupts 299
10.3 Output Compare 300
Output Compare Time Delays 305
Output Compare Interrupts 307
Output Compare Bit Operation 309
One Output Compare Controlling up to Eight Outputs 315
Very Short Duration Pulses 317
Forced Output Compares 317
Output Compare Software Check-list 319
10.4 Input Capture 320
Input Capture Software Check-list 323
10.5 Pulse Accumulator 323
Pulse Accumulator Interrupts 326
10.6 Plain and Fancy Timing 326
10.7 Real-time Interrupt 328
10.8 Timer Input and Output Electronics 331
10.9 External Interrupts Using Timer Interrupts 331
10.10 Clearing Timer Flags 331
Fast Timer Flag Clearing 333
10.11 MC68HC912B32 Pulse-width Modulator 333
Pulse-width Modulator Clock Control 336
Pulse-width Modulation Control Registers 337
Other Pulse-width Modulation Registers 344
Choosing Pulse-width Modulation Counter Prescaler Values 345
10.12 Conclusion and Chapter Summary Points 350
10.13 Problems 351
CHAPTER 11. M68HC12 SERIAL I/O
11.1 Introduction 353
11.2 Port S Serial I/O 353
11.3 Asynchronous Serial Communications Interface - SCI 355
SCI Data 355
SCI Initialization 357
SCI Status Flags 364
SCI Interrupts 366
SCI Wake Up 368
SCI Break Character 370
Port S SCI I/O 370
SCI Programming Example 371
11.4 Synchronous Serial Peripheral Interface - SPI 373
Interprocessor Serial Communications 374
SPI Data Register 374
SPI Initialization 375
SPI Master and Slave Modes 377
SPI Data Rate and Clock Formats 380
SPI Status Register and Interrupts 382
SPI Interrupts 383
SPI Programming Example 383
11.5 MC68HC912B32 Byte Data Link Communications Module 386
BDLC Modes 386
BDLC Loopback Testing 387
BDLC Control Registers 387
BDLC J1850 Bus Errors 395
11.6 Conclusion and Chapter Summary Points 395
11.7 Bibliography and Further Reading 397
11.8 Problems 397
CHAPTER 12. M68HC12 ANALOG INPUT
12.1 Introduction 399
12.2 M68HC12 A/D Converter 399
A/D Initialization 401
A/D Operation 407
Digital Results from the A/D 409
12.3 A/D Input Synchronization 410
Polling A/D Conversion Complete 410
Clearing Status Flags 411
12.4 A/D Interrupts 412
12.5 Miscellaneous A/D Registers 413
12.6 A/D Control Register Summary 415
12.7 A/D Programming Summary 415
12.8 A/D Programming Example 416
12.9 Chapter Summary Points 419
12.10 Bibliography and Further Reading 419
12.11 Problems 419
CHAPTER 13. FUZZY LOGIC
13.1 Introduction 421
13.2 Our Digital Heritage 422
13.3 How is Fuzzy Logic Different? 423
13.4 What is Fuzzy About Fuzzy Logic? 424
13.5 Structure of a Fuzzy Logic Inference Program 425
13.6 Fuzzification 428
13.7 Rule Evaluation 431
13.8 Defuzzification 434
13.9 Putting it all Together 436
13.10 The Complete Fuzzy Inference System 437
13.11 Fuzzy Logic 440
Fuzzy Logic Instructions 440
Minimum and Maximum Instructions 447
Table Lookup Instructions 447
13.12 Conclusion and Chapter Summary Points 449
13.13 Bibliography and Further Reading 449
13.14 Problems 449
CHAPTER 14. DEBUGGING SYSTEMS
14.1 Introduction 451
Some Debugging Definitions and Terms 452
14.2 Development Related Features of the M68HC12 452
14.3 Hardware Versus Software Breakpoints 453
SWI-based Software Breakpoints 453
BGND-based Software Breakpoints 454
Hardware Breakpoints 454
14.4 Background Debug Module 455
Single-wire Physical Interface 455
Special-mode Select Function 456
Tagging Function 456
Background Communication Function 457
Serial Commands 459
BDM Registers 462
More Complex Commands 464
Chip-level BDM Details 465
Active BDM Entry Sequence Details 466
Active BDM Exit Sequence Details 467
Implementing a BDM POD 468
Application uses for BDM 468
14.5 Instruction Tagging 470
Using the Tagging Function 470
14.6 Capturing M68HC12 Bus Signals 471
The M68HC12 Instruction Queue (Pipeline) 474
Cycle-by-cycle Mnemonic Codes 479
Working with Bus State Information 479
14.7 Hardware Breakpoints 486
Breakpoint Module Registers and Control Bits 486
Breakpoint Uses 492
ROM Patching 493
14.8 Conclusion and Chapter Summary Points 502
14.9 Bibliography and Further Reading 503
14.10 Problems 503
CHAPTER 15. ADVANCED M68HC12 HARDWARE
15.1 M68HC12 Clock Generators 506
Basic Clock Generators 506
MC68HC812A4 Sysclk Generator 507
MC68HC912B32 Sysclk Generator 508
Other System Clocks 509
Phase-locked Loop 510
External Clock Oscillator 516
15.2 Hardware Mode Select 516
Normal Operating Modes 516
Special Operating Modes 517
15.3 Expanded Mode Port E Emulation 517
15.4 Miscellaneous Registers 518
15.5 Power Saving Modes 519
Using a Slow Clock 519
Using the WAI and STOP Instructions 520
Disabling Unneeded Circuits 521
15.6 Bibliography and Further Reading 521
APPENDIX A: DEBUGGING SYSTEMS POD DESIGN 567
ANSWERS TO CHAPTER PROBLEMS 583
INDEX 599